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PALs and CPLDs

Programmable Array Logic and CPLDs (Complex Programmable Logic Devices) achieve very low delay in return for simple, nearly fixed, wiring structure.

All expressions are expanded to SOP form with limited number of products.


A typical PAL with 7 inputs and 7 I/Os.

Contents of the example PAL macrocell.
   pin 16 = o1;
   pin 2 = a;
   pin 3 = b;
   pin 4 = c

   o1.oe = ~a;
   o1 = (b & o1) | c;

   -x-- ---- ---- ---- ---- ---- ----  (oe term)
   --x- x--- ---- ---- ---- ---- ----  (pin 3 and 16)
   ---- ---- x--- ---- ---- ---- ----  (pin 4)
   xxxx xxxx xxxx xxxx xxxx xxxx xxxx
   xxxx xxxx xxxx xxxx xxxx xxxx xxxx
   xxxx xxxx xxxx xxxx xxxx xxxx xxxx
   xxxx xxxx xxxx xxxx xxxx xxxx xxxx
   xxxx xxxx xxxx xxxx xxxx xxxx xxxx
   x                                   (macrocell fuse)

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.