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T Dynamic Power Gating

Previously we looked at dynamic clock gating, but we can also turn off power supply to regions of a chip, allbeit with coarser grain. We use power gating cells in series with supply rails.

Use signal isolation and retention cells (t-latches) on nets that cross in and out of the region. There is no register and RAM data retention in a block while the power is off. This technique is most suitable for complete sub-systems of a chip, that are not in use on a particular product or for quite a long time, such as a bluetooth tranceiver or audio input ADC.

Generally, power off/on is controlled by software or top-level input pads to the SoC. It requires some sequencing to activate the enables to the retention cells in the correct order and hence several clock cycles or more are needed to power up/down a region.

A common pracite is to power off a whole chip except for a one or two RAMs and register files. This was particularly common before FLASH memory was invented, when a small battery is/was used retain contents using a lower supply (CMOS RAM data holding voltage). Today, most mobile phones and PC mother cards have a second, tiny battery that maintains a small amout of logic when the main power is off or battery removed. This can run the real-time clock (RTC) as well.

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.