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Dynamic Clock Gating Continued: When to clock?

How to generate clock enable conditions ?

A clock is `needed' if any register will change on a clock edge.

Can get expensive ? So compute once at head of a pipeline...

Need to be sure there are no `oscillating' stages or else know their settling time.

Save further power: shortly we look at dynamic frequency and voltage scaling.

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.