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Other on-chip busses.

The AMBA AHB bus from ARM Cambridge was widely used: but is quite complex and has no temporal decoupling.

The BVCI supports temporal decoupling, but requests and responses must not overtake: hence it can cross clock domains and tolerate pipeline stages.

The ARM AXI bus includes tags on each operation for request/response association: hence it is suitable for pipelined, on-chip networks.

The Wishbone bus and IBM CoreConnect bus: used by various public domain IP bocks and various designs in the OpenCores project. »Wikipedia Wishbone »Core Connect

The OSCI TLM2.0 generic payload and the GreenSocs bus are higher-level specifications, perhaps with future vision of automatic synthesis of all glue logic?

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.