SoC Component, TLM Form Example DMA Controller

The RTL coding style of the DMA controller shown earlier was a little bit hard to understand, but at least it was synthesisable.

The active component of an ESL version of such a DMA controller is simply:

  // Bus mastering side 
  while(1)
  { 
    waituntil(busy);
    while (length-- > 0)
      mem.write(dest++, mem.read(src++));
    busy = 0;
  }

In other words, it looks just like a simple block copy in C++. (Full details are in the practical class examples.)

However, we can see that that memory operations are likely to get well out of synchronisation with the real system since this copying loop just goes as fast as it can without worrying about the speed of the real hardware. It is just governed by the number of cycles the read and write calls block for, which could be none. The whole block copy might occur in zero simulation time!

This sort of modelling is useful for exposing certain types of bugs in a design, but it does not give useful performance feedback.