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Counters and Timers

  reg [31:0] prescale, prescalar;
  reg [31:0] counter, reload;
  reg int_enable, ovf, int_pending;
  always @(posedge clk) begin
     ovf <= (prescale == prescalar);
     prescale <= (ovf) ? 0: prescale+1; 
     if (ovf) counter <= counter -1;
     if (counter == 0) begin
         int_pending <= 1;
         counter <= reload;
     if (host_op) int_pending <= 0;
  wire host_op = hwen && addr == 32;
  assign interrupt = int_pending && int_enable;
Re-load register accommodates poor interrupt latency.

Timer (illustrated in RTL) : counts pre-scaled system clock. Counter: counts external event pulses (e.g. car rev counter).

Four to eight, versatile, configurable counter/timers provided in one block (only one shown in RTL).

All registers also configured as bus target read/write resources.

Interrupt cleared by host programmed I/O to host_op.

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.