The framestore reads out the contents of its frame buffer again and again. The memory is implemented in a Verilog array and this has two address ports. Another approach is to have a single address port and for the RAM to be simply 'stolen' from the output device when the host makes a write to it. This will cause noticable display artefacts if writes are at all frequent.
This framestore has fixed resolution, but real ones have programmable values read from registers instead of the fixed numbers 230 and 110.
The framestore in this example has its own local RAM. This reduces RAM bandwidth costs on the main RAM but uses more silicon area. A delicate trade off! A typical compromise, also used on audio and other DSP I/O, is to have a small staging RAM or FIFO in the actual device but to keep as much as possible in the main memory.
It's an output only device that never goes bust, so it generates no interrupts.