A commonly-requried component for basic synchronisation between separate cores.
Offers a target (slave interface) for one ore more cores. Generates interrupts for the other cores (and self in symmetric situations).
One core write a register that assers and interrupt wire to another core.
Mailbox variant allows small data items to be written to a queue in the interrupter. These are read out by the (or any) core that is (or wants to) handle the interrupt.