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Clock Domain Crossing Bridge

Like a bus bridge, but different clocks on each side.

  • Have one signal that is a guard or qualifier signal for all the others going in that direction.
  • Make sure all the other signals are settled in advance of guard.
  • Pass the guard signal through two registers before using it (metastability).
  • Use a wide bus (crossing operations less frequent).

   input clk;  // receiving domain clock
   input [31..0] data; 
   input req;
   output reg ack;

reg [31:0] captured_data; reg r1, r2; always @(posedge clk) begin r1 <= req; r2 <= r1; ack <= r2; if (r2 && !ack) captured_data <= data;

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.