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Toy Class 5 : Multiple Bus Masters

The new component for this class is the bus arbiter in TLM/ESL form »tlm_busarb.h.

Aim: The aim of this class is to see that the bus arbiter is tivial in TLM form, especially when untimed.

Two instances of the nominal processor are connected to one bus.

The ESL-style bus arbiter implements no queueing and allows more than one thread to block in the target at once, but exclusion should be added to model more-realistic sharing.

Exercise: Introduce some timing or other accounting into the TLM bus aribiter and see if similar answers are as prediced by fluid-flow/spreadsheet style analysis. Experienced RTL designers may wish to implement an RTL-style arbiter and compare answers with that.

Class 5: Provided Compilation Targets

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.