RTL Synthesis: Summary
- Ignore all timing information (hash delays),
- Generate a pure RTL list of assignments for each clock domain,
- A final list represents combinational logic, not associated with a clock domain,
- Convert arithmetic operators to logical operators or instantiate structural instances (e.g. multipliers, adders and RAMs),
- Code generate for each bit lane: match operations needed against available library of gates.
(Similar to a software compiler: match operations needed against instruction set.)