System-on-Chip Design and Modelling

Lecturer: Dr D.J. Greaves
No. of lectures: 12
Prerequisite courses: Specification and Verification II, Computer Design, ECAD, C and C++


A current-day system on a chip (SoC) consists of several different microprocessor subsystems together with memories and I/O interfaces. This course covers SoC design and modelling techniques with emphasis on architectural exploration, assertion-driven design and the concurrent development of hardware and embedded software. This is the ``front end'' of the design automation tool chain. (Back end material, such as design of individual gates, layout, routing and fabrication of silicon chips is not covered.)

A percentage of each lecture is used to develop a running example. Over the course of the lectures, the example evolves into a System On Chip demonstrator with CPU and bus models, device models and device drivers. All code and tools are available online so the examples can be reproduced and exercises undertaken. The main languages used are Verilog and C++ using the SystemC library.


In addition to these topics, the running example will demonstrate a few practical aspects of device bus interface design, on chip communication and device control software. Students are encouraged to try out and expand the examples in their own time.


At the end of the course students should

Recommended reading

* OSCI. SystemC tutorials and whitepapers . Download from OSCI or copy from course web site (to be added below).

Ghenassia, F. (2006). Transaction-level modeling with SystemC: TLM concepts and applications for embedded systems . Springer.

Eisner, C. & Fisman, D. (2006). A practical introduction to PSL . Springer (Series on Integrated Circuits and Systems).

Foster, H.D. & Krolnik, A.C. (2008). Creating assertion-based IP . Springer (Series on Integrated Circuits and Systems).

Grotker, T., Liao, S., Martin, G. & Swan, S. (2002). System design with SystemC . Springer.\\ Wolf, W. (2002). Modern VLSI design (System-on-chip design) . Pearson Education. LINK.

Additional Materials

To be added.