We will cover many of the following topics:
1.Verilog RTL Design with examples. Basic RTL to gates synthesis algorithm.
2. Further examples. Event-driven simulation cycle. Using signals, variables and transactions for component inter-communication.
3. SystemC overview. Verilog synthesis and high/low-level mapping examples.
4. High-level modelling in SystemC. Bus and cache structures, DRAM interface. Design exploration.
5. Transactional modelling (ESL). Electronic systems level design. IP- XACT.
6. Processor Modelling. Instruction set simulators, cache modelling and hybrid models.
7. Assertions and Monitors. System Verilog brief tour. PSL/SVA assertions. Temporal logic compilation to FSM. Assertion-based design.
8. On Chip Interconnect. Busses (OPB (BVCI) and AXI). Glue logic synthesis. Transactor Synthesis. Network on chip.