If we have the following:
always @(posedge clk) v <= 1; always @(posedge clk) v <= 0;
we have a non-deterministic design (banned for synthesis).
Exercise: Here's a more interesting example:
always @(posedge clk) begin v1 = v1 + 10; v2 = v3; end assign v3 = v1 + 1;
What happens here: does the continuous assignment get executed between the assignments of v1 and v2 ?