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Structural Hazards in RTL

A structural hazard in an RTL design can make it non synthesisable.

Consider the following expressions:

   q <= Foo[x] + Foo[y];
   q <= Foo[Foo[v]];
   q <= a*b + c*d;

Problems arising:

(A flash multiplier is a combinational circuit that computes in less than one clock cycle).

In addition, the RAMs may be synchronous with fixed latency and the multiplication time might be data dependent. The multipliers might not be fully-pipelined.

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.