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Don't care states in HDL.

Verilog allows specification of don't cares as shown in this (ALU-like) example:

  wire [31:0] my_output = 
         (case1) ? a + b: 
         (case2) ? ~a: 
         (case3) ? a - b:

Here we are asserting that if none of the case signals is true, then we do not care what the value on the bus `my_output' is. These don't care values will become fuel to the logic minimiser. (If you try this with cv2 you will find cv2 has a second-rate logic minimiser.) Advanced Verilog programmers will know how to tell the compiler other facts, such as that `case1' and `case2' will never be true at the same time, which will also cause logic simplification to be possible (such information creates further, effective dont-care points).