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Synthesis goals: logic minimisation, delay area, power.

There are many digital logic circuits which achieve the same function, but they vary in

Typically minimisation aims to reduce the number of gates, but wiring can be reduced at the expense of gates if a gate is duplicated with identical inputs at the points where its output is needed, provided those inputs are available locally.

Speed optimisation is a valuable technique. Typically, many paths are given `<em> dont-exceed</em>' timespecs (timing specifications). The optimiser must select a pattern of gates which meets these timespecs. The paths may be specified as start-end pairs or else, for sequential logic, as `<em> must-be-stable</em>' times relative to the clock.