So that components can be interconnected easily, automatic synthesis of glue logic is a critical future development. A standardised interconnect format should allow bus creation to be fully automated. The bandwidth budget of a bus depends on the number of data wires used and the number of devices attached. It may be pipelined, giving various latencies of access. In the future, the user should just express the bandwidth budget and the interconnections should be synthesised, provided each component has been designed to a standardised interface paradigm. The paradigm could be a first-class component of the HDL.
A standard EDA interconnection networking system can also usefully serve as the partition between different modelling styles. For instance, a system simulation may involve a mixture of gate-level modelling, behavioural models and cycle-accurate models. Each style of simulation might have variations in how accurately it represents time. A standard interconnection network would support flow control so that variations in timing can be accommodated, but the total number and ordering of 'transactions' between models would be preserved.