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Motivations to do better.
Verilog and VHDL have allowed vast ASICs to be designed, so in some
sense they are successful. But improved languages are needed to meet the
following EDA aims:
- Speed of design: time to market,
- Facilitate richer behavioural specification,
- Readily allow time/space folding experiments,
- Greater freedom and hence scope for optimisation in the compiler,
- Facilitate implementation of a formal specification,
- Facilitate proof of conformance to a specification,
- Allow rule-based programming (i.e.\ a logic-programming sub-language),
- Support modern synchronisation primitives (e.g.\ join patterns)
- Portability: can be compiled into software as well as into hardware.