Hands-on with the NetFPGA
John W. Lockwood,
Andrew W. Moore,
to build a Gigabit-rate Router
Monday, March 31, 2008
9am - 5pm
Department of Computer Science,
Room 422, Forth floor,
Sir Alwyn Williams Building,
18 Lilybank Gardens, Glasgow G12 8QQ
An open platform called the NetFPGA
has been developed at Stanford University.
The NetFPGA platform enables researchers and instructors to
build high-speed, hardware-accelerated networking systems.
The platform can be used in the classroom to teach students how to build
Ethernet switches and Internet Protocol (IP) routers using hardware
rather than software. The platform can be used by researchers to prototype
advanced services for next-generation networks.
By using Field Programmable Gate Arrays (FPGAs),
the NetFPGA enables new types of packet routing circuits to be
implemented and detailed measurements of network traffic to be obtained.
During the tutorial, we will use the NetFPGA to determine
the amount of memory needed to buffer TCP/IP data streaming through
the Gigabit/second router.
Hardware circuits within the NetFPGA will be implemented
to measure and plot the occupancy of buffers.
Circuits will be downloaded into reconfigurable hardware and tested with live,
streaming Internet video traffic.
Attendees will utilise a Linux-based PC equipped with NetFPGA hardware.
A basic understanding of Ethernet switching and network routing is expected.
Past experience with Verilog is useful but not required.
This full-day tutorial emulates the successful one-day held at Hot Interconnects
and builds upon the half-day tutorial at SIGMETRICS'07.
from that event as well as a description of the NetFPGA Platform
are available on-line from the
- Function of an Internet Router
- Control plane
- Routing protocols
- Routing table
- Management and Command Line Interface (CLI)
- Address lookup
- Longest prefix match
- Classless Interdomain Routing (CIDR)
- Header update
- Packet buffer
- NetFPGA Router
- Gigabit Ethernet interfaces
- PCI host interface
- Field Programmable Gate Array (FPGA) Logic
- Random Access Memory (RAM)
- Kernel-space driver
- User-space applications
- System configuration
- Demonstration Topology
- Network of ten routers
- Ethernet switch
- Video server
- High Definition (HD) video client
- Routing tables
- Dynamic re-routing
- Integrated Circuit Design
- Look-Up Tables (LUTs)
- Configurable Logic Blocks (CLBs)
- Field Programmable Gate Arrays (FPGAs)
- Verilog Hardware Description Language (HDL)
- Registers, integers, arrays
- Synchronous storage elements
- Finite State Machines (FSMs)
- Hardware Debug
- Waveform monitor
- In-circuit logic emulation
- NetFPGA System Components
- Synthesis of tutorial router
- Java-based Graphical User Interface (GUI)
- Router architecture
- Buffer Size Experiment
- Experiment with TCP/IP flows
- Rule-of-thumb for the buffer size
- Round-trip propagation delay
- Capacity of bottleneck link
- Number of active flows
- Lower delay with smaller queues
- Enhanced Router
- Additional hardware
- Event capture module
- Rate limiter
- Delay module
- HD video transport
- Life of packet through the system
- Description of blocks
- Waveforms from logic analyser
About the presenters
- John W. Lockwood
John W. Lockwood is a Visiting Associate Professor at Stanford University. At Stanford, he is working to develop new applications for the NetFPGA platform.
Lockwood's research interests include reconfigurable hardware, Internet security, and content processing technologies.
Dr. Lockwood earned his MS, BS, and Ph.D degrees from the Department of Electrical and Computer Engineering at the University of Illinois. Lockwood was granted tenure in the Department of Computer Science and Engineering at Washington University in Saint Louis in 2006. At Washington University in St. Louis, Lockwood led the Reconfigurable Network Group (RNG) to develop the Field programmable Port Extender (FPX) to enable rapid prototype of extensible network modules in Field Programmable Gate Array (FPGA) technology.
John Lockwood has served as the principal investigator on grants from
the US National Science Foundation, Xilinx, Altera, Nortel Networks, Rockwell Collins, and Boeing. He has worked in industry for AT&T Bell Laboratories, IBM, Science Applications International Corporation (SAIC), and the National Center for Supercomputing Applications (NCSA). He served as a co-founder of Global Velocity, a networking startup company focused on high-speed data security. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.
Andrew W. Moore is a Lecturer at the University
of Cambridge Computer Laboratory. He joined the permanent faculty of
Cambridge in 2007, prior to this he had been an EPSRC Roberts Fellow
at Queen Mary, University of London, an Intel Research Fellow in
Cambridge and foundation-researcher at the Cambridge Marconi research
laboratory. Throughout this time Andrew has focused upon network
characterisation and measurement, extensible monitoring for
application performance-analysis and large-scale Internet monitoring
and emulation. Interest in switch design has led to work in physical
line-coding for optical networks, and novel optical-switch
Andrew completed his Ph.D. with the Cambridge University Computer
Laboratory in 2001 and prior to that took a Masters degree and an
honours degree from Monash University in Melbourne. Australia. Alongside routine collaboration with AT&T, Endace, Intel, and
Microsoft, Andrew Moore has served as principal investigator on grants
from the UK Research Council (EPSRC) and a number of UK government
bodies. He is a chartered engineer with the IET and a member of the
IEEE, ACM and USENIX.
- Adam Covington
is a Research Associate of the
High-Performance Network Group (HPN) at Stanford University. Adam is
currently working on the NetFPGA project. Previously, he was a Research
Associate with the Reconfigurable Network Group (RNG) at Washington
University in St. Louis. Adam's research interests include
reconfigurable systems, artificial intelligence (clustering and
classification), and applications of artificial intelligence algorithms.
Upon completing a Bachelor of Science degree in Computer Engineering in
2003, Adam earned his Masters of Science degree in Computer Science and
Engineering from Washington University in December of 2006.
- Registration for the tutorial is now on-line from the link
on the EuroSys 2008 website.
- The NetFPGA tutorial is part of the Affiliated
Workshop Program. The registration page is here.
(Including revision notes)
A Bill of
Materials is available for the PC used at the Eurosys 2008