The UIA processor is used in two ways as a concrete example in the HPR-L/S project. It is an example both of microprocessor synthesis and for code generation for a conventional processor architecture.
The architecture is defined using the following SML constants and is easily changed for experiments: UIA.txt. These constants describe the instruction set encoding and operational semantics.
The HPR tool can emit processor desings in a number of output formats, including Verilog RTL, SystemC, NuSMV and even in machine code for itself, so it can simulate itself on an instance of itself.
The C-like subset of the H2 language enables C programs to be readily compiled for the processor and so is a route for HW/SW co-synthesis. The HPR kiwic tool currently takes CIL (.net) bytecode and generates hardware designs in SystemC, RTL and machine code for the UIA custom processor.
The primes program looks like this when compiled for this architecture: listing.txt.
The first plot shows part of the the execution of the primes program when the processor is implemented as high-level RTL.
The second plot shows the same code execution, but on a version of the processor where the memory is held in a single-ported RAM, accessed by the AD, RD, WR and WEN signals. The timescale is expanded because the port is multiplexed between code fetch and data access.
Similar variations in execution time occur if the number of ports on the register file is adjusted.