// CBG Orangepath HPRLS System

// Verilog output file generated at Tue Aug 12 21:51:46 BST 2008

// Kiwic: HPR Orange IL/.net front end: Version alpha 18: 13-Jul-08

// -root primes;primes.Main -vnl primes.vnl -preserve-sequencer 1 


module primes(reset, clk, primes_count, primes_vol);
input reset;
  input clk;
  output [31:0] primes_count;
  input [31:0] primes_vol;
  integer primes_Main_Main_V_0;
  integer primes_Main_Main_V_1;
  integer primes_Main_Main_V_2;
  integer primes_Main_Main_V_3;
  reg [2:0] primesMain10pc;
  reg PA__10000_9719397[9999:0];
  reg [31:0] primes_count;
  integer primes_limit;
   always @(posedge clk) begin //Start Hpr/ls
          if (reset) primesMain10pc <= 0;
           else 
          case (primesMain10pc)
          
          0:  begin primesMain10pc <= 1;
                 PA__10000_9719397[0] <= 0<primes_vol;
                 primes_count <= 0;
                 primes_Main_Main_V_0 <= 0;
                 $display("%s%d", "Primes Up To ", 10000);
                 
                 
                  end 
          1:  begin if (9999<=primes_Main_Main_V_0) primesMain10pc <= 2;
                 if (primes_Main_Main_V_0<9999) 
                   begin PA__10000_9719397[primes_Main_Main_V_0] <= 1;
                      primes_Main_Main_V_0 <= primes_Main_Main_V_0+1;
                      
                       end if (9999<=primes_Main_Main_V_0) 
                   begin PA__10000_9719397[primes_Main_Main_V_0] <= 1;
                      primes_Main_Main_V_0 <= primes_Main_Main_V_0+1;
                      primes_Main_Main_V_1 <= 2;
                      
                       end 
                  end 
          2:  begin if (primes_Main_Main_V_1*2<10000) primesMain10pc <= 3;
                 if (10000<=primes_Main_Main_V_1*2 && 9999<=primes_Main_Main_V_1) primesMain10pc <= 4;
                 if (primes_Main_Main_V_1*2<10000) primes_Main_Main_V_2 <= primes_Main_Main_V_1*2;
                 if (10000<=primes_Main_Main_V_1*2 && primes_Main_Main_V_1<9999) 
                   begin primes_Main_Main_V_2 <= primes_Main_Main_V_1*2;
                      primes_Main_Main_V_1 <= primes_Main_Main_V_1+1;
                      
                       end if (10000<=primes_Main_Main_V_1*2 && 9999<=primes_Main_Main_V_1) 
                   begin primes_Main_Main_V_2 <= primes_Main_Main_V_1*2;
                      primes_Main_Main_V_1 <= primes_Main_Main_V_1+1;
                      primes_Main_Main_V_3 <= 0;
                      
                       end 
                  end 
          3:  begin if (10000<=primes_Main_Main_V_2+primes_Main_Main_V_1 && primes_Main_Main_V_1<9999) primesMain10pc <= 2;
                 if (10000<=primes_Main_Main_V_2+primes_Main_Main_V_1 && 9999<=primes_Main_Main_V_1) primesMain10pc <= 4;
                 if (primes_Main_Main_V_2+primes_Main_Main_V_1<10000) 
                   begin PA__10000_9719397[primes_Main_Main_V_2] <= 0;
                      primes_Main_Main_V_2 <= primes_Main_Main_V_2+primes_Main_Main_V_1;
                      
                       end if (10000<=primes_Main_Main_V_2+primes_Main_Main_V_1 && primes_Main_Main_V_1<9999) 
                   begin PA__10000_9719397[primes_Main_Main_V_2] <= 0;
                      primes_Main_Main_V_2 <= primes_Main_Main_V_2+primes_Main_Main_V_1;
                      primes_Main_Main_V_1 <= primes_Main_Main_V_1+1;
                      
                       end if (10000<=primes_Main_Main_V_2+primes_Main_Main_V_1 && 9999<=primes_Main_Main_V_1) 
                   begin PA__10000_9719397[primes_Main_Main_V_2] <= 0;
                      primes_Main_Main_V_2 <= primes_Main_Main_V_2+primes_Main_Main_V_1;
                      primes_Main_Main_V_1 <= primes_Main_Main_V_1+1;
                      primes_Main_Main_V_3 <= 0;
                      
                       end 
                  end 
          4:  begin if (!(PA__10000_9719397[primes_Main_Main_V_3]) && 9999<=primes_Main_Main_V_3) primesMain10pc <= 5;
                 if (!(!(PA__10000_9719397[primes_Main_Main_V_3])) && 9999<=primes_Main_Main_V_3) primesMain10pc <= 5;
                 if (!(PA__10000_9719397[primes_Main_Main_V_3]) && primes_Main_Main_V_3<9999) primes_Main_Main_V_3 <= primes_Main_Main_V_3+1;
                 if (!(PA__10000_9719397[primes_Main_Main_V_3]) && 9999<=primes_Main_Main_V_3) primes_Main_Main_V_3 <= primes_Main_Main_V_3+1;
                 if (!(!(PA__10000_9719397[primes_Main_Main_V_3])) && primes_Main_Main_V_3<9999) 
                   begin primes_count <= primes_count+1;
                      primes_Main_Main_V_3 <= primes_Main_Main_V_3+1;
                      
                       end if (!(!(PA__10000_9719397[primes_Main_Main_V_3])) && 9999<=primes_Main_Main_V_3) 
                   begin primes_count <= primes_count+1;
                      primes_Main_Main_V_3 <= primes_Main_Main_V_3+1;
                      $display("There are %d primes below the natural number %d.", primes_count+1, 10000);
                      
                      
                       end if (!(PA__10000_9719397[primes_Main_Main_V_3]) && 9999<=primes_Main_Main_V_3) $display("There are %d primes below the natural number %d."
                 , primes_count, 10000);
                 
                 
                  end 
          5:  begin 
                  end endcase
          //End Hpr/ls


           end 
          // Start delx primes_Main10
  // End delx primes_Main10


  endmodule

// eof (hprls verilog)