// CBG Orangepath HPRLS System // Verilog output file generated at Tue Aug 12 19:28:35 BST 2008 // Kiwic: HPR Orange IL/.net front end: Version alpha 18: 13-Jul-08 // -root primes;primes.Main -vnl primes.vnl -preserve-sequencer 1 -restructure BVCI module primes(reset, clk, primes_count, primes_vol, Pa_rdata, Pa_rerror, Pa_reop, Pa_rspack, Pa_rspval, Pa_be, Pa_addr, Pa_wdata, Pa_eop, Pa_cmd, Pa_plen, Pa_cmdval, Pa_cmdack); input reset; input clk; output [31:0] primes_count; input [31:0] primes_vol; input [31:0] Pa_rdata; input Pa_rerror; input Pa_reop; output Pa_rspack; input Pa_rspval; output [3:0] Pa_be; output [31:0] Pa_addr; output [31:0] Pa_wdata; output Pa_eop; output [1:0] Pa_cmd; output [6:0] Pa_plen; output Pa_cmdval; input Pa_cmdack; reg stall; reg [15:0] PAHOLDING10; integer primes_Main_Main_V_0; integer primes_Main_Main_V_1; integer primes_Main_Main_V_2; integer primes_Main_Main_V_3; reg [3:0] primesMain10pc; reg [31:0] primes_count; integer primes_limit; reg Pa_rspack; reg [3:0] Pa_be; reg [31:0] Pa_addr; reg [31:0] Pa_wdata; reg Pa_eop; reg [1:0] Pa_cmd; reg [6:0] Pa_plen; reg Pa_cmdval; always @(posedge clk) begin //Start Hpr/ls //End Hpr/ls // Next line added by hand $display("pc=%d v0=%d V1=%d v2=%d", primesMain10pc, primes_Main_Main_V_0, primes_Main_Main_V_1, primes_Main_Main_V_2); //Start Hpr/ls if (reset) stall <= 0; else stall <= 0&!reset; //End Hpr/ls //Start Hpr/ls if (reset) primesMain10pc <= 0; else case (primesMain10pc) 0: begin if (Pa_cmdack) begin primesMain10pc <= 1; Pa_rspack <= 1; Pa_cmd <= 2; Pa_addr <= 0; Pa_cmdval <= 1; Pa_wdata <= 0