// CBG Orangepath HPR/LS System

// Verilog output file generated at 5/4/2011 8:54:58 AM
// KiwiC (.net/CIL/C# to Verilog/SystemC compiler): Version alpha 53c: 29-Apr-11 Unix 2.6.32.26
//  /home/djg11/d320/hprls/kiwic/distro/lib/kiwic.exe -report-each-step -techno=disable -csharp=dut.cs -restructure2=disable -cpp=disable -csharp-gen=disable test4.exe /home/djg11/d320/hprls/kiwic/distro/support/Kiwi.dll /home/djg11/d320/hprls/kiwic/distro/support/Kiwic.dll -finish true -root test4;test4.Main -vnl DUT.v -sim 3000 -simtl 0

module DUT(reset,  clk,  din,  dout);
  input reset;
  input clk;
  input din;
  output dout;
  reg signed [31:0] DRSX32SS_AX_CC_SOL_QC_SOL[8:0];
  integer mpc10;
  integer Ttar0_3_V_6;
  integer Ttar0_3_V_4;
  integer Ttar0_3_V_3;
  integer Ttar0_3_V_1;
  integer Ttar0_3_V_0;
 always   @(posedge clk )  begin 
      //Start HPR test4.exe
      if (reset)  begin 
               Ttar0_3_V_0 <= 32'd0;
               Ttar0_3_V_3 <= 32'd0;
               Ttar0_3_V_6 <= 32'd0;
               Ttar0_3_V_4 <= 32'd0;
               Ttar0_3_V_1 <= 32'd0;
               mpc10 <= 32'd0;

               end 
               else  begin 
               case (mpc10)
              2/*2:mpc10XS:":pcIS44:AG"*/:  begin 
                  if ((Ttar0_3_V_6<8)) if (!(!(DRSX32SS_AX_CC_SOL_QC_SOL[1+Ttar0_3_V_6]%2)))  begin 
                               mpc10 <= 4/*4:mpc10XS:":pcIS63:AG"*/;
                               Ttar0_3_V_0 <= 1+Ttar0_3_V_0;
                               Ttar0_3_V_4 <= DRSX32SS_AX_CC_SOL_QC_SOL[1+Ttar0_3_V_6];
                               end 
                               else  begin 
                               Ttar0_3_V_1 <= 1+Ttar0_3_V_1;
                               Ttar0_3_V_4 <= DRSX32SS_AX_CC_SOL_QC_SOL[1+Ttar0_3_V_6];
                               end 
                               else mpc10 <= 8/*8:mpc10XS:":pcIS56:AG"*/;

                           Ttar0_3_V_6 <= 1+Ttar0_3_V_6;
                           Ttar0_3_V_3 <= 1+Ttar0_3_V_3;
                          $write("%d i=%d: ", Ttar0_3_V_3, Ttar0_3_V_4);
                          $display("so far %d Odd Numbers, and %d Even Numbers.", Ttar0_3_V_0, Ttar0_3_V_1);
                          if ((Ttar0_3_V_6>=8))
                             $display("Found %d Odd Numbers, and %d Even Numbers.", Ttar0_3_V_0, Ttar0_3_V_1);
                   end 
                  
              4/*4:mpc10XS:":pcIS63:AG"*/:  begin 
                  if ((Ttar0_3_V_6<8)) if (!(!(DRSX32SS_AX_CC_SOL_QC_SOL[1+Ttar0_3_V_6]%2)))  begin 
                               Ttar0_3_V_0 <= 1+Ttar0_3_V_0;
                               end 
                               else  begin 
                               mpc10 <= 2/*2:mpc10XS:":pcIS44:AG"*/;
                               Ttar0_3_V_1 <= 1+Ttar0_3_V_1;
                               end 
                               else mpc10 <= 8/*8:mpc10XS:":pcIS56:AG"*/;
                           Ttar0_3_V_4 <= DRSX32SS_AX_CC_SOL_QC_SOL[1+Ttar0_3_V_6];
                           Ttar0_3_V_6 <= 1+Ttar0_3_V_6;
                           Ttar0_3_V_3 <= 1+Ttar0_3_V_3;
                          $write("%d i=%d: ", Ttar0_3_V_3, Ttar0_3_V_4);
                          $display("so far %d Odd Numbers, and %d Even Numbers.", Ttar0_3_V_0, Ttar0_3_V_1);
                          if ((Ttar0_3_V_6>8)) 
                          $display("Found %d Odd Numbers, and %d Even Numbers.", Ttar0_3_V_0, Ttar0_3_V_1);
                          
                   end 
                  
              8/*8:mpc10XS:":pcIS56:AG"*/: $finish(0);
              endcase
              if ((0==mpc10))  begin 
                       mpc10 <= 2/*2:mpc10XS:":pcIS44:AG"*/;
                       Ttar0_3_V_1 <= 1;
                       Ttar0_3_V_4 <= 0;
                       Ttar0_3_V_6 <= 0;
                       Ttar0_3_V_3 <= 0;
                       Ttar0_3_V_0 <= 0;
                       DRSX32SS_AX_CC_SOL_QC_SOL[2] <= 2;
                       DRSX32SS_AX_CC_SOL_QC_SOL[7] <= 2021;
                       DRSX32SS_AX_CC_SOL_QC_SOL[5] <= 8;
                       DRSX32SS_AX_CC_SOL_QC_SOL[3] <= 5;
                       DRSX32SS_AX_CC_SOL_QC_SOL[1] <= 1;
                       DRSX32SS_AX_CC_SOL_QC_SOL[0] <= 0;
                       DRSX32SS_AX_CC_SOL_QC_SOL[4] <= 7;
                       DRSX32SS_AX_CC_SOL_QC_SOL[6] <= 1121;
                       DRSX32SS_AX_CC_SOL_QC_SOL[8] <= 2048;
                       end 
                      if ((mpc10==8/*8:mpc10XS:":pcIS56:AG"*/))  mpc10 <= 1/*1:mpc10XS:":pcIS-10:AG"*/;
               end 
              //End HPR test4.exe
       end 
// 9 array locations of width 32
// 192 bits in scalar variables
// Total state bits in module = 480 bits.
endmodule
// eof (HPR/LS Verilog)