// CBG Orangepath HPR/LS System // Verilog output file generated at 5/5/2011 10:08:10 PM // KiwiC (.net/CIL/C# to Verilog/SystemC compiler): Version alpha 53c: 29-Apr-11 Unix 2.6.34.7 // /home/djg11/d320/hprls/kiwic/distro/lib/kiwic.exe -report-each-step -techno=disable -csharp=dut.cs -restructure2=enable -csharp-gen=disable test4.exe /home/djg11/d320/hprls/kiwic/distro/support/Kiwi.dll /home/djg11/d320/hprls/kiwic/distro/support/Kiwic.dll -finish true -root test4;test4.Main -vnl DUT.v -sim 3000 -simtl 0 module DUT( reset, clk, din, dout); input reset; input clk; input din; output dout; reg [31:0] DRSX32SS_AX_CC_SOL_QC_SOL_WRD0; reg DRSX32SS_AX_CC_SOL_QC_SOL_REN0; reg DRSX32SS_AX_CC_SOL_QC_SOL_WEN0; reg [31:0] DRSX32SS_AX_CC_SOL_QC_SOL_registered_AD0; reg [31:0] DRSX32SS_AX_CC_SOL_QC_SOL_RDD0; reg [3:0] mpc10zz; reg [31:0] DRSX32SS_AX_CC_SOL_QC_SOL_AD0; reg signed [31:0] DRSX32SS_AX_CC_SOL_QC_SOL[8:0]; integer mpc10; integer Ttar0_3_V_6; integer Ttar0_3_V_4; integer Ttar0_3_V_3; integer Ttar0_3_V_1; integer Ttar0_3_V_0; reg [31:0] DRSXSSAXCCSOLQCSOLholda10; reg [31:0] DRSXSSAXCCSOLQCSOLholda12; reg Hstall10; // Start HPR HPR_RAM_1_32 // End HPR HPR_RAM_1_32 always @(posedge clk ) begin //Start HPR test4.exe if (reset) begin Ttar0_3_V_0 <= 32'd0; Ttar0_3_V_3 <= 32'd0; Ttar0_3_V_6 <= 32'd0; Ttar0_3_V_4 <= 32'd0; Ttar0_3_V_1 <= 32'd0; end else begin if (!Hstall10 && (mpc10==2/*2:mpc10XS:":pcIS44:AG"*/)) if ((Ttar0_3_V_6<8)) begin $write("%d i=%d: ", Ttar0_3_V_3, Ttar0_3_V_4); $display("so far %d Odd Numbers, and %d Even Numbers.", Ttar0_3_V_0, Ttar0_3_V_1); end else begin $write("%d i=%d: ", Ttar0_3_V_3, Ttar0_3_V_4); $display("so far %d Odd Numbers, and %d Even Numbers.", Ttar0_3_V_0, Ttar0_3_V_1); $display("Found %d Odd Numbers, and %d Even Numbers.", Ttar0_3_V_0, Ttar0_3_V_1); end if (!Hstall10 && (mpc10==4/*4:mpc10XS:":pcIS63:AG"*/)) if ((Ttar0_3_V_6<8)) begin $write("%d i=%d: ", Ttar0_3_V_3, Ttar0_3_V_4); $display("so far %d Odd Numbers, and %d Even Numbers.", Ttar0_3_V_0, Ttar0_3_V_1); end else begin $write("%d i=%d: ", Ttar0_3_V_3, Ttar0_3_V_4); $display("so far %d Odd Numbers, and %d Even Numbers.", Ttar0_3_V_0, Ttar0_3_V_1); $display("Found %d Odd Numbers, and %d Even Numbers.", Ttar0_3_V_0, Ttar0_3_V_1); end if (!Hstall10 && (mpc10==8/*8:mpc10XS:":pcIS56:AG"*/)) $finish(0); if (!Hstall10 && (mpc10==4/*4:mpc10XS:":pcIS63:AG"*/)) if ((Ttar0_3_V_6<8)) if (!(!(DRSXSSAXCCSOLQCSOLholda12%2))) begin Ttar0_3_V_0 <= 1+Ttar0_3_V_0; Ttar0_3_V_4 <= DRSXSSAXCCSOLQCSOLholda12; Ttar0_3_V_6 <= 1+Ttar0_3_V_6; Ttar0_3_V_3 <= 1+Ttar0_3_V_3; end else begin Ttar0_3_V_1 <= 1+Ttar0_3_V_1; Ttar0_3_V_4 <= DRSXSSAXCCSOLQCSOLholda12; Ttar0_3_V_6 <= 1+Ttar0_3_V_6; Ttar0_3_V_3 <= 1+Ttar0_3_V_3; end else begin Ttar0_3_V_6 <= 1+Ttar0_3_V_6; Ttar0_3_V_3 <= 1+Ttar0_3_V_3; end if (!Hstall10 && (mpc10==2/*2:mpc10XS:":pcIS44:AG"*/)) if ((Ttar0_3_V_6<8)) if (!(!(DRSXSSAXCCSOLQCSOLholda10 %2))) begin Ttar0_3_V_0 <= 1+Ttar0_3_V_0; Ttar0_3_V_4 <= DRSXSSAXCCSOLQCSOLholda10; Ttar0_3_V_6 <= 1+Ttar0_3_V_6; Ttar0_3_V_3 <= 1+Ttar0_3_V_3; end else begin Ttar0_3_V_1 <= 1+Ttar0_3_V_1; Ttar0_3_V_4 <= DRSXSSAXCCSOLQCSOLholda10; Ttar0_3_V_6 <= 1+Ttar0_3_V_6; Ttar0_3_V_3 <= 1+Ttar0_3_V_3; end else begin Ttar0_3_V_6 <= 1+Ttar0_3_V_6; Ttar0_3_V_3 <= 1+Ttar0_3_V_3; end if (!Hstall10 && (0==mpc10)) begin Ttar0_3_V_1 <= 1; Ttar0_3_V_4 <= 0; Ttar0_3_V_6 <= 0; Ttar0_3_V_3 <= 0; Ttar0_3_V_0 <= 0; end end if (reset) begin DRSX32SS_AX_CC_SOL_QC_SOL_registered_AD0 <= 32'd0; mpc10zz <= 4'd0; mpc10 <= 32'd0; Ttar0_3_V_1 <= 32'd0; Ttar0_3_V_4 <= 32'd0; Ttar0_3_V_6 <= 32'd0; Ttar0_3_V_3 <= 32'd0; Ttar0_3_V_0 <= 32'd0; Hstall10 = 1'd0; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = 32'd0; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = 1'd0; DRSXSSAXCCSOLQCSOLholda10 = 32'd0; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = 32'd0; DRSXSSAXCCSOLQCSOLholda12 = 32'd0; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = 1'd0; end else begin case (mpc10zz) 0/*0:mpc10zz*/: begin mpc10zz <= 1/*1:mpc10zz*/; Hstall10 = 0; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = DRSX32SS_AX_CC_SOL_QC_SOL_WRD0; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = DRSX32SS_AX_CC_SOL_QC_SOL_WEN0; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = 8; DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end 1/*1:mpc10zz*/: begin mpc10zz <= 2/*2:mpc10zz*/; Hstall10 = 1; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = 2048; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = 1; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = 6; DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end 2/*2:mpc10zz*/: begin mpc10zz <= 3/*3:mpc10zz*/; Hstall10 = 1; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = 1121; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = 1; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = 4; DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end 3/*3:mpc10zz*/: begin mpc10zz <= 4/*4:mpc10zz*/; Hstall10 = 1; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = 7; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = 1; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = 0; DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end 4/*4:mpc10zz*/: begin mpc10zz <= 5/*5:mpc10zz*/; Hstall10 = 1; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = 0; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = 1; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = 1; DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end 5/*5:mpc10zz*/: begin mpc10zz <= 6/*6:mpc10zz*/; Hstall10 = 1; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = 1; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = 1; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = 3; DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end 6/*6:mpc10zz*/: begin mpc10zz <= 7/*7:mpc10zz*/; Hstall10 = 1; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = 5; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = 1; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = 5; DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end 7/*7:mpc10zz*/: begin mpc10zz <= 8/*8:mpc10zz*/; Hstall10 = 1; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = 8; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = 1; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = 7; DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end 8/*8:mpc10zz*/: begin mpc10zz <= 9/*9:mpc10zz*/; Hstall10 = 1; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = 2021; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = 1; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = 2; DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end 9/*9:mpc10zz*/: begin mpc10 <= 2/*2:mpc10XS:":pcIS44:AG"*/; mpc10zz <= 10/*10:mpc10zz*/; Hstall10 = 1; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = 2; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = 1; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = 1+(Hstall10? Ttar0_3_V_6: 0); DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end 10/*10:mpc10zz*/: begin mpc10 <= ((Ttar0_3_V_6>=8)? 8/*8:mpc10XS:":pcIS56:AG"*/: (!(!(DRSXSSAXCCSOLQCSOLholda10%2)) && (Ttar0_3_V_6<8)? 4/*4:mpc10XS:":pcIS63:AG"*/: (!(DRSXSSAXCCSOLQCSOLholda10 %2) && (Ttar0_3_V_6<8)? 2/*2:mpc10XS:":pcIS44:AG"*/: mpc10))); mpc10zz <= ((Ttar0_3_V_6>=8)? 12/*12:mpc10zz*/: (!(!(DRSXSSAXCCSOLQCSOLholda10%2)) && (Ttar0_3_V_6<8)? 11/*11:mpc10zz*/: (!(DRSXSSAXCCSOLQCSOLholda10 %2) && (Ttar0_3_V_6<8)? 10/*10:mpc10zz*/: mpc10zz))); Hstall10 = 0; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = DRSX32SS_AX_CC_SOL_QC_SOL_WRD0; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = DRSX32SS_AX_CC_SOL_QC_SOL_WEN0; DRSXSSAXCCSOLQCSOLholda10 = DRSX32SS_AX_CC_SOL_QC_SOL_RDD0; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = ((Ttar0_3_V_6<8)? 1+(!Hstall10? 1+Ttar0_3_V_6: Ttar0_3_V_6): DRSX32SS_AX_CC_SOL_QC_SOL_AD0 ); DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = (Ttar0_3_V_6<8); end 11/*11:mpc10zz*/: begin mpc10 <= ((Ttar0_3_V_6>=8)? 8/*8:mpc10XS:":pcIS56:AG"*/: (!(DRSXSSAXCCSOLQCSOLholda12%2) && (Ttar0_3_V_6<8)? 2/*2:mpc10XS:":pcIS44:AG"*/: (!(DRSXSSAXCCSOLQCSOLholda12 %2) || (Ttar0_3_V_6>=8)? mpc10: (!(!(DRSXSSAXCCSOLQCSOLholda12%2)) && (Ttar0_3_V_6<8)? 4: 1)))); mpc10zz <= ((Ttar0_3_V_6>=8)? 12/*12:mpc10zz*/: (!(DRSXSSAXCCSOLQCSOLholda12%2) && (Ttar0_3_V_6<8)? 10/*10:mpc10zz*/: (!(!(DRSXSSAXCCSOLQCSOLholda12 %2)) && (Ttar0_3_V_6<8)? 11/*11:mpc10zz*/: mpc10zz))); Hstall10 = 0; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = DRSX32SS_AX_CC_SOL_QC_SOL_WRD0; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = DRSX32SS_AX_CC_SOL_QC_SOL_WEN0; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = ((Ttar0_3_V_6<8)? 1+(!Hstall10? 1+Ttar0_3_V_6: Ttar0_3_V_6): DRSX32SS_AX_CC_SOL_QC_SOL_AD0 ); DRSXSSAXCCSOLQCSOLholda12 = DRSX32SS_AX_CC_SOL_QC_SOL_RDD0; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = (Ttar0_3_V_6<8); end 12/*12:mpc10zz*/: begin mpc10 <= 1/*1:mpc10XS:":pcIS-10:AG"*/; mpc10zz <= 13/*13:mpc10zz*/; Hstall10 = 0; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = DRSX32SS_AX_CC_SOL_QC_SOL_WRD0; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = DRSX32SS_AX_CC_SOL_QC_SOL_WEN0; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = DRSX32SS_AX_CC_SOL_QC_SOL_AD0; DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end 13/*13:mpc10zz*/: begin Hstall10 = 0; mpc10 <= 1; mpc10zz <= 13/*13:mpc10zz*/; DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 = DRSX32SS_AX_CC_SOL_QC_SOL_WRD0; DRSX32SS_AX_CC_SOL_QC_SOL_WEN0 = DRSX32SS_AX_CC_SOL_QC_SOL_WEN0; DRSXSSAXCCSOLQCSOLholda10 = DRSXSSAXCCSOLQCSOLholda10; DRSX32SS_AX_CC_SOL_QC_SOL_AD0 = DRSX32SS_AX_CC_SOL_QC_SOL_AD0; DRSXSSAXCCSOLQCSOLholda12 = DRSXSSAXCCSOLQCSOLholda12; DRSX32SS_AX_CC_SOL_QC_SOL_REN0 = DRSX32SS_AX_CC_SOL_QC_SOL_REN0; end endcase Ttar0_3_V_0 <= (!Hstall10 && (!(!(DRSXSSAXCCSOLQCSOLholda12%2))? (!(!(DRSXSSAXCCSOLQCSOLholda10%2))? (Ttar0_3_V_6<8) && ((mpc10==2/*2:mpc10XS:":pcIS44:AG"*/) || (mpc10==4/*4:mpc10XS:":pcIS63:AG"*/)): (Ttar0_3_V_6<8) && (mpc10==4/*4:mpc10XS:":pcIS63:AG"*/)): !(!(DRSXSSAXCCSOLQCSOLholda10 %2)) && (Ttar0_3_V_6<8) && (mpc10==2/*2:mpc10XS:":pcIS44:AG"*/))? 1+Ttar0_3_V_0: (Hstall10 || (0!=mpc10)? Ttar0_3_V_0: 0 )); Ttar0_3_V_3 <= (!Hstall10 && ((mpc10==2/*2:mpc10XS:":pcIS44:AG"*/) || (mpc10==4/*4:mpc10XS:":pcIS63:AG"*/))? 1+Ttar0_3_V_3 : (Hstall10 || (0!=mpc10)? Ttar0_3_V_3: 0)); Ttar0_3_V_6 <= (!Hstall10 && ((mpc10==2/*2:mpc10XS:":pcIS44:AG"*/) || (mpc10==4/*4:mpc10XS:":pcIS63:AG"*/))? 1+Ttar0_3_V_6 : (Hstall10 || (0!=mpc10)? Ttar0_3_V_6: 0)); Ttar0_3_V_4 <= (!Hstall10 && (Ttar0_3_V_6<8) && (mpc10==4/*4:mpc10XS:":pcIS63:AG"*/)? DRSXSSAXCCSOLQCSOLholda12: (!Hstall10 && (Ttar0_3_V_6<8) && (mpc10==2/*2:mpc10XS:":pcIS44:AG"*/)? DRSXSSAXCCSOLQCSOLholda10: (Hstall10 || (0!=mpc10)? Ttar0_3_V_4 : 0))); Ttar0_3_V_1 <= (!Hstall10 && (!(!(DRSXSSAXCCSOLQCSOLholda12%2))? !(DRSXSSAXCCSOLQCSOLholda10%2) && (Ttar0_3_V_6<8) && (mpc10==2/*2:mpc10XS:":pcIS44:AG"*/): (!(!(DRSXSSAXCCSOLQCSOLholda10%2))? (Ttar0_3_V_6<8) && (mpc10==4/*4:mpc10XS:":pcIS63:AG"*/): (Ttar0_3_V_6 <8) && ((mpc10==2/*2:mpc10XS:":pcIS44:AG"*/) || (mpc10==4/*4:mpc10XS:":pcIS63:AG"*/))))? 1+Ttar0_3_V_1: (Hstall10 || (0 !=mpc10)? Ttar0_3_V_1: 1)); DRSX32SS_AX_CC_SOL_QC_SOL_registered_AD0 <= DRSX32SS_AX_CC_SOL_QC_SOL_AD0; end //End HPR test4.exe //Start HPR HPR_RAM_1_32 if (!reset) begin if (DRSX32SS_AX_CC_SOL_QC_SOL_WEN0) DRSX32SS_AX_CC_SOL_QC_SOL[DRSX32SS_AX_CC_SOL_QC_SOL_registered_AD0] <= DRSX32SS_AX_CC_SOL_QC_SOL_WRD0 ; end //End HPR HPR_RAM_1_32 end always @(*) DRSX32SS_AX_CC_SOL_QC_SOL_RDD0 = DRSX32SS_AX_CC_SOL_QC_SOL[DRSX32SS_AX_CC_SOL_QC_SOL_registered_AD0]; // // 3 vectors of width 1 // 1 vectors of width 4 // 6 vectors of width 32 // 9 array locations of width 32 // 192 bits in scalar variables // Total state bits in module = 679 bits. endmodule // eof (HPR/LS Verilog)