// Verilog output file generated at 26/04/2016 12:22:17 // Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 2.03: Feb-2016 Unix 3.13.0.65 // /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe seven-segment.exe -vnl-roundtrip=disable -vnl-resets=synchronous -restructure2=disable -vnl=seven-segment.v -vnl-rootmodname=DUT module DUT(input clear, output reg [31:0] segments, output reg [31:0] strobes, input clk, input reset); integer seven_segment_digit_on_display; integer sTMT4Main_V_0; integer Tsre2_0_V_0; integer Tssc3_5_V_0; integer Tsin4_0_V_0; integer Tsin4_0_V_1; reg signed [31:0] A_SINT_CC_SCALbx10_ARA0[4:0]; reg signed [31:0] A_SINT_CC_SCALbx12_ARB0[10:0]; // THIS IS NORMALLY A ROM! reg [8:0] xpc10; always @(posedge clk ) begin //Start structure HPR seven-segment.exe if (reset) begin Tsre2_0_V_0 <= 32'd0; segments <= 32'd0; strobes <= 32'd0; seven_segment_digit_on_display <= 32'd0; Tsin4_0_V_1 <= 32'd0; sTMT4Main_V_0 <= 32'd0; Tsin4_0_V_0 <= 32'd0; xpc10 <= 9'd0; Tssc3_5_V_0 <= 32'd0; end else begin case (xpc10) 0/*0:US*/: begin xpc10 <= 1'd1/*1:xpc10:1*/; sTMT4Main_V_0 <= 32'd0; seven_segment_digit_on_display <= 32'd0; A_SINT_CC_SCALbx10_ARA0[2'd3] <= 32'd0; A_SINT_CC_SCALbx10_ARA0[2'd2] <= 32'd0; A_SINT_CC_SCALbx10_ARA0[1'd1] <= 32'd0; A_SINT_CC_SCALbx10_ARA0[0] <= 32'd0; A_SINT_CC_SCALbx12_ARB0[4'd10] <= 32'd126; A_SINT_CC_SCALbx12_ARB0[4'd9] <= 32'd12; A_SINT_CC_SCALbx12_ARB0[4'd8] <= 32'd0; A_SINT_CC_SCALbx12_ARB0[3'd7] <= 32'd15; A_SINT_CC_SCALbx12_ARB0[3'd6] <= 32'd96; A_SINT_CC_SCALbx12_ARB0[3'd5] <= 32'd36; A_SINT_CC_SCALbx12_ARB0[3'd4] <= 32'd76; A_SINT_CC_SCALbx12_ARB0[2'd3] <= 32'd6; A_SINT_CC_SCALbx12_ARB0[2'd2] <= 32'd18; A_SINT_CC_SCALbx12_ARB0[1'd1] <= 32'd79; A_SINT_CC_SCALbx12_ARB0[0] <= 32'd1; end 1'd1/*1:US*/: if (clear) begin xpc10 <= 2'd2/*2:xpc10:2*/; Tsre2_0_V_0 <= 32'd0; end else xpc10 <= 3'd4/*4:xpc10:4*/; 2'd2/*2:US*/: if ((Tsre2_0_V_0<3'd4)) begin Tsre2_0_V_0 <= 32'd1+Tsre2_0_V_0; A_SINT_CC_SCALbx10_ARA0[Tsre2_0_V_0] <= 32'd0; end else xpc10 <= 3'd4/*4:xpc10:4*/; 3'd4/*4:US*/: begin xpc10 <= 4'd8/*8:xpc10:8*/; Tssc3_5_V_0 <= 32'd0; segments <= A_SINT_CC_SCALbx12_ARB0[A_SINT_CC_SCALbx10_ARA0[32'hffffffff&((1'd1+seven_segment_digit_on_display )%3'd4)]]; strobes <= (32'd1<<(5'd31&32'hffffffff&((1'd1+seven_segment_digit_on_display)%3'd4))); seven_segment_digit_on_display <= ((1'd1+seven_segment_digit_on_display)%3'd4); sTMT4Main_V_0 <= 32'd1+sTMT4Main_V_0; end 4'd8/*8:US*/: begin if ((Tssc3_5_V_0>=3'd4) && (sTMT4Main_V_0==4'd10/*10:US*/)) begin xpc10 <= 5'd16/*16:xpc10:16*/; Tsin4_0_V_0 <= 32'd0; end if ((Tssc3_5_V_0>=3'd4) && (sTMT4Main_V_0!=4'd10/*10:US*/)) xpc10 <= 7'd64/*64:xpc10:64*/; if ((Tssc3_5_V_0<3'd4)) xpc10 <= 9'd256/*256:xpc10:256*/; end 5'd16/*16:US*/: begin if ((Tsin4_0_V_0<3'd4) && (4'd10/*10:MS*/!=(32'hffffffff&Tsin4_0_V_0+A_SINT_CC_SCALbx10_ARA0[Tsin4_0_V_0]))) begin xpc10 <= 8'd128/*128:xpc10:128*/; Tsin4_0_V_1 <= Tsin4_0_V_0+A_SINT_CC_SCALbx10_ARA0[Tsin4_0_V_0]; end if ((Tsin4_0_V_0<3'd4) && (4'd10/*10:MS*/==(32'hffffffff&Tsin4_0_V_0+A_SINT_CC_SCALbx10_ARA0[Tsin4_0_V_0 ]))) begin xpc10 <= 8'd128/*128:xpc10:128*/; Tsin4_0_V_1 <= 32'd0; end if ((Tsin4_0_V_0>=3'd4)) xpc10 <= 6'd32/*32:xpc10:32*/; end 6'd32/*32:US*/: begin xpc10 <= 7'd64/*64:xpc10:64*/; sTMT4Main_V_0 <= 32'd0; end 8'd128/*128:US*/: if (!(!Tsin4_0_V_1)) begin xpc10 <= 6'd32/*32:xpc10:32*/; A_SINT_CC_SCALbx10_ARA0[Tsin4_0_V_0] <= 32'hffffffff&Tsin4_0_V_1; end else begin xpc10 <= 5'd16/*16:xpc10:16*/; Tsin4_0_V_0 <= 32'd1+Tsin4_0_V_0; A_SINT_CC_SCALbx10_ARA0[Tsin4_0_V_0] <= 32'hffffffff&Tsin4_0_V_1; end 9'd256/*256:US*/: begin xpc10 <= 4'd8/*8:xpc10:8*/; Tssc3_5_V_0 <= 32'd1+Tssc3_5_V_0; end endcase if ((xpc10==7'd64/*64:US*/)) xpc10 <= 1'd1/*1:xpc10:1*/; end //End structure HPR seven-segment.exe end // 1 vectors of width 9 // 192 bits in scalar variables // Total state bits in module = 1033 bits. // Total number of leaf cells = 0 endmodule