// Verilog output file generated at 29/04/2016 12:11:41
// Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 2.03c Interim: 25-Apr-2016 Unix 3.13.0.65
//  /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe seven-segment.exe -vnl-roundtrip=disable -vnl-resets=synchronous -vnl=seven-segment.v -vnl-rootmodname=DUT

module DUT(input clear, output reg [31:0] segments, output reg [31:0] strobes, input clk, input reset);
  reg signed [31:0] A_SINT_CC_SCALbx12_ARB0[10:0];
  integer seven_segment_digit_on_display;
  integer sTMT4Main_V_0;
  integer Tsre2_0_V_0;
  integer Tssc3_5_V_0;
  integer Tsin4_0_V_0;
  integer Tsin4_0_V_1;
  reg signed [31:0] A_SINT_CC_SCALbx10_ARA0[3:0];
  reg [31:0] A_SINT_CC_SCALbx12_ARB0_RDD0;
  reg [3:0] A_SINT_CC_SCALbx12_ARB0_AD0;
  reg A_SINT_CC_SCALbx12_ARB0_REN0;
  reg xpc10_stall;
  wire xpc10_clear;
  reg [31:0] SINTCCSCALbx12ARB0RRh10hold;
  reg SINTCCSCALbx12ARB0RRh10shot0;
  reg [3:0] xpc10nz;
  always @(* )  begin 
       A_SINT_CC_SCALbx12_ARB0_AD0 = 0;
       A_SINT_CC_SCALbx12_ARB0_REN0 = 0;
      if (!xpc10_stall)  begin 
               A_SINT_CC_SCALbx12_ARB0_REN0 = ((xpc10nz==3'd7/*7:US*/)? 1'd1: 1'd0);
              if ((xpc10nz==3'd7/*7:US*/))  A_SINT_CC_SCALbx12_ARB0_AD0 = A_SINT_CC_SCALbx10_ARA0[32'hffffffff&((1'd1+seven_segment_digit_on_display
                  )%3'd4)];

                   end 
               end 
      

 always   @(posedge clk )  begin 
      //Start structure HPR @_SINT/CC/SCALbx12_ARB0
      if (reset)  A_SINT_CC_SCALbx12_ARB0_RDD0 <= 32'd0;
           else  A_SINT_CC_SCALbx12_ARB0_RDD0 <= A_SINT_CC_SCALbx12_ARB0[A_SINT_CC_SCALbx12_ARB0_AD0];
      //End structure HPR @_SINT/CC/SCALbx12_ARB0


      //Start structure HPR seven-segment.exe
      if (reset)  begin 
               Tsre2_0_V_0 <= 32'd0;
               strobes <= 32'd0;
               segments <= 32'd0;
               Tsin4_0_V_1 <= 32'd0;
               Tsin4_0_V_0 <= 32'd0;
               Tssc3_5_V_0 <= 32'd0;
               seven_segment_digit_on_display <= 32'd0;
               sTMT4Main_V_0 <= 32'd0;
               SINTCCSCALbx12ARB0RRh10hold <= 32'd0;
               SINTCCSCALbx12ARB0RRh10shot0 <= 1'd0;
               xpc10nz <= 4'd0;
               end 
               else  begin 
              if (!xpc10_stall) 
                  case (xpc10nz)
                      0/*0:US*/:  begin 
                           seven_segment_digit_on_display <= 32'd0;
                           sTMT4Main_V_0 <= 32'd0;
                           A_SINT_CC_SCALbx10_ARA0[2'd3] <= 32'd0;
                           A_SINT_CC_SCALbx10_ARA0[2'd2] <= 32'd0;
                           A_SINT_CC_SCALbx10_ARA0[1'd1] <= 32'd0;
                           A_SINT_CC_SCALbx10_ARA0[0] <= 32'd0;
                           end 
                          
                      1'd1/*1:US*/:  Tssc3_5_V_0 <= 32'd1+Tssc3_5_V_0;

                      3'd4/*4:US*/:  sTMT4Main_V_0 <= 32'd0;

                      4'd8/*8:US*/:  begin 
                           strobes <= (32'd1<<(5'd31&32'hffffffff&((1'd1+seven_segment_digit_on_display)%3'd4)));
                           segments <= A_SINT_CC_SCALbx12_ARB0_RDD0;
                           Tssc3_5_V_0 <= 32'd0;
                           seven_segment_digit_on_display <= ((1'd1+seven_segment_digit_on_display)%3'd4);
                           sTMT4Main_V_0 <= 32'd1+sTMT4Main_V_0;
                           end 
                          endcase
                  if ((xpc10nz==0/*0:US*/))  xpc10nz <= 4'd10/*10:xpc10nz*/;
                  if (SINTCCSCALbx12ARB0RRh10shot0 && (xpc10nz==4'd8/*8:US*/))  xpc10nz <= 3'd6/*6:xpc10nz*/;
                  
              case (xpc10nz)
                  2'd2/*2:US*/:  begin 
                      if (!(!Tsin4_0_V_1))  begin 
                              if (!(!Tsin4_0_V_1) && !xpc10_stall)  A_SINT_CC_SCALbx10_ARA0[Tsin4_0_V_0] <= 32'hffffffff&Tsin4_0_V_1;
                                   xpc10nz <= 3'd4/*4:xpc10nz*/;
                               end 
                               else  begin 
                              if (!Tsin4_0_V_1 && !xpc10_stall)  A_SINT_CC_SCALbx10_ARA0[Tsin4_0_V_0] <= 32'hffffffff&Tsin4_0_V_1;
                                   xpc10nz <= 3'd5/*5:xpc10nz*/;
                               end 
                              if (!Tsin4_0_V_1 && !xpc10_stall)  Tsin4_0_V_0 <= 32'd1+Tsin4_0_V_0;
                           end 
                      
                  3'd5/*5:US*/:  begin 
                      if ((Tsin4_0_V_0<3'd4))  xpc10nz <= 2'd2/*2:xpc10nz*/;
                           else  xpc10nz <= 3'd4/*4:xpc10nz*/;
                      if ((Tsin4_0_V_0<3'd4) && (4'd10/*10:MS*/==(32'hffffffff&Tsin4_0_V_0+A_SINT_CC_SCALbx10_ARA0[Tsin4_0_V_0])) && 
                      !xpc10_stall)  Tsin4_0_V_1 <= 32'd0;
                          if ((Tsin4_0_V_0<3'd4) && (4'd10/*10:MS*/!=(32'hffffffff&Tsin4_0_V_0+A_SINT_CC_SCALbx10_ARA0[Tsin4_0_V_0])) && 
                      !xpc10_stall)  Tsin4_0_V_1 <= Tsin4_0_V_0+A_SINT_CC_SCALbx10_ARA0[Tsin4_0_V_0];
                           end 
                      
                  3'd6/*6:US*/:  begin 
                      if ((Tssc3_5_V_0>=3'd4) && (sTMT4Main_V_0==4'd10/*10:US*/) && !xpc10_stall)  Tsin4_0_V_0 <= 32'd0;
                          if ((Tssc3_5_V_0>=3'd4) && (sTMT4Main_V_0==4'd10/*10:US*/))  xpc10nz <= 3'd5/*5:xpc10nz*/;
                          if ((Tssc3_5_V_0>=3'd4) && (sTMT4Main_V_0!=4'd10/*10:US*/))  xpc10nz <= 2'd3/*3:xpc10nz*/;
                          if ((Tssc3_5_V_0<3'd4))  xpc10nz <= 1'd1/*1:xpc10nz*/;
                           end 
                      
                  4'd9/*9:US*/:  begin 
                      if ((Tsre2_0_V_0<3'd4))  begin 
                              if ((Tsre2_0_V_0<3'd4) && !xpc10_stall)  A_SINT_CC_SCALbx10_ARA0[Tsre2_0_V_0] <= 32'd0;
                                   xpc10nz <= 4'd9/*9:xpc10nz*/;
                               end 
                               else  xpc10nz <= 3'd7/*7:xpc10nz*/;
                      if ((Tsre2_0_V_0<3'd4) && !xpc10_stall)  Tsre2_0_V_0 <= 32'd1+Tsre2_0_V_0;
                           end 
                      
                  4'd10/*10:US*/:  begin 
                      if (clear)  xpc10nz <= 4'd9/*9:xpc10nz*/;
                           else  xpc10nz <= 3'd7/*7:xpc10nz*/;
                      if (clear && !xpc10_stall)  Tsre2_0_V_0 <= 32'd0;
                           end 
                      endcase
              if (SINTCCSCALbx12ARB0RRh10shot0)  SINTCCSCALbx12ARB0RRh10hold <= A_SINT_CC_SCALbx12_ARB0_RDD0;
                  
              case (xpc10nz)
                  1'd1/*1:US*/:  xpc10nz <= 3'd6/*6:xpc10nz*/;

                  3'd4/*4:US*/:  xpc10nz <= 2'd3/*3:xpc10nz*/;
              endcase
               SINTCCSCALbx12ARB0RRh10shot0 <= (xpc10nz==3'd7/*7:US*/) && !xpc10_stall;
              if ((xpc10nz==2'd3/*3:US*/))  xpc10nz <= 4'd10/*10:xpc10nz*/;
                  if ((xpc10nz==3'd7/*7:US*/))  xpc10nz <= 4'd8/*8:xpc10nz*/;
                   end 
              //End structure HPR seven-segment.exe


       end 
      

  always @(*) xpc10_stall = !SINTCCSCALbx12ARB0RRh10shot0 && (xpc10nz==4'd8/*8:US*/);
  initial        begin 
      //ROM data table: 11 words of 32 bits.
       A_SINT_CC_SCALbx12_ARB0[0] = 32'h1;
       A_SINT_CC_SCALbx12_ARB0[1] = 32'h4f;
       A_SINT_CC_SCALbx12_ARB0[2] = 32'h12;
       A_SINT_CC_SCALbx12_ARB0[3] = 32'h6;
       A_SINT_CC_SCALbx12_ARB0[4] = 32'h4c;
       A_SINT_CC_SCALbx12_ARB0[5] = 32'h24;
       A_SINT_CC_SCALbx12_ARB0[6] = 32'h60;
       A_SINT_CC_SCALbx12_ARB0[7] = 32'hf;
       A_SINT_CC_SCALbx12_ARB0[8] = 32'h0;
       A_SINT_CC_SCALbx12_ARB0[9] = 32'hc;
       A_SINT_CC_SCALbx12_ARB0[10] = 32'h7e;
       end 
      

// 2 vectors of width 4
// 3 vectors of width 1
// 2 vectors of width 32
// 15 array locations of width 32
// 192 bits in scalar variables
// Total state bits in module = 747 bits.
// 1 continuously assigned (wire/non-state) bits 
// Total number of leaf cells = 0
endmodule