// CBG Orangepath HPR/LS System // Verilog output file generated at 16/05/2012 13:21:39 // KiwiC (.net/CIL/C# to Verilog/SystemC compiler): Version alpha 54j: 20th-December-2011 Unix 2.6.32.34 // /home/djg11/d320/hprls/kiwic/distro/lib/kiwic.exe -onehot-pc=false i2c_control.exe -vnl i2c_control.v -sim 1000 module i2c_control(input checker, input i2c_sda_in, output reg i2c_scl_openable, output reg i2c_sda_openable, output reg i2c_sda_out, output reg i2c_scl_out, output reg done, input clk, input reset); integer TCISe0_22_V_0; integer TCISe0_22_V_1; integer TCISe0_29_V_0; integer TCISe0_29_V_1; integer TCISe0_31_V_0; integer TCISe0_31_V_1; reg [10:0] xpc10; always @(posedge clk ) begin //Start HPR i2c_control.exe if (reset) begin TCISe0_22_V_0 <= 32'd0; TCISe0_22_V_1 <= 32'd0; TCISe0_29_V_0 <= 32'd0; TCISe0_29_V_1 <= 32'd0; TCISe0_31_V_0 <= 32'd0; TCISe0_31_V_1 <= 32'd0; i2c_scl_openable <= 1'd0; i2c_sda_openable <= 1'd0; i2c_sda_out <= 1'd0; i2c_scl_out <= 1'd0; done <= 1'd0; xpc10 <= 11'd0; end else begin case (xpc10) 0/*0:bashint*/: $display("Start condition"); 3/*3:bashint*/: $display("Sending device ID"); endcase if ((1>=TCISe0_22_V_1) && (xpc10==6/*6:bashint*/)) $display("Indicate write operation."); case (xpc10) 9/*9:bashint*/: $display("Processing ACK"); 13/*13:bashint*/: $display("Sending device register address"); endcase if ((1>=TCISe0_29_V_1) && (xpc10==16/*16:bashint*/)) $display("Processing ACK"); if ((1>=TCISe0_31_V_1) && (xpc10==23/*23:bashint*/)) $display("Processing ACK"); case (xpc10) 27/*27:bashint*/: $display("Generate stop condition."); 30/*30:bashint*/: $display("Start condition"); 33/*33:bashint*/: $display("Sending device ID"); endcase if ((1>=TCISe0_22_V_1) && (xpc10==36/*36:bashint*/)) $display("Indicate write operation."); case (xpc10) 39/*39:bashint*/: $display("Processing ACK"); 43/*43:bashint*/: $display("Sending device register address"); endcase if ((1>=TCISe0_29_V_1) && (xpc10==46/*46:bashint*/)) $display("Processing ACK"); if ((1>=TCISe0_31_V_1) && (xpc10==53/*53:bashint*/)) $display("Processing ACK"); case (xpc10) 57/*57:bashint*/: $display("Generate stop condition."); 60/*60:bashint*/: $display("Start condition"); 63/*63:bashint*/: $display("Sending device ID"); endcase if ((1>=TCISe0_22_V_1) && (xpc10==66/*66:bashint*/)) $display("Indicate write operation."); case (xpc10) 69/*69:bashint*/: $display("Processing ACK"); 73/*73:bashint*/: $display("Sending device register address"); endcase if ((1>=TCISe0_29_V_1) && (xpc10==76/*76:bashint*/)) $display("Processing ACK"); if ((1>=TCISe0_31_V_1) && (xpc10==83/*83:bashint*/)) $display("Processing ACK"); if ((xpc10==87/*87:bashint*/)) $display("Generate stop condition."); if (checker && (xpc10==90/*90:bashint*/)) $display("Start condition"); if ((xpc10==93/*93:bashint*/)) $display("Sending device ID"); if ((1>=TCISe0_22_V_1) && (xpc10==96/*96:bashint*/)) $display("Indicate write operation."); case (xpc10) 99/*99:bashint*/: $display("Processing ACK"); 103/*103:bashint*/: $display("Sending device register address"); endcase if ((1>=TCISe0_29_V_1) && (xpc10==106/*106:bashint*/)) $display("Processing ACK"); if ((1>=TCISe0_31_V_1) && (xpc10==113/*113:bashint*/)) $display("Processing ACK"); if ((xpc10==117/*117:bashint*/)) $display("Generate stop condition."); if (checker && (xpc10==121/*121:bashint*/)) $display("Start condition"); if ((xpc10==124/*124:bashint*/)) $display("Sending device ID"); if ((1>=TCISe0_22_V_1) && (xpc10==127/*127:bashint*/)) $display("Indicate write operation."); case (xpc10) 130/*130:bashint*/: $display("Processing ACK"); 134/*134:bashint*/: $display("Sending device register address"); endcase if ((1>=TCISe0_29_V_1) && (xpc10==137/*137:bashint*/)) $display("Processing ACK"); if ((1>=TCISe0_31_V_1) && (xpc10==144/*144:bashint*/)) $display("Processing ACK"); if ((xpc10==148/*148:bashint*/)) $display("Generate stop condition."); if (checker && (xpc10==152/*152:bashint*/)) $display("Start condition"); if ((xpc10==155/*155:bashint*/)) $display("Sending device ID"); if ((1>=TCISe0_22_V_1) && (xpc10==158/*158:bashint*/)) $display("Indicate write operation."); case (xpc10) 161/*161:bashint*/: $display("Processing ACK"); 165/*165:bashint*/: $display("Sending device register address"); endcase if ((1>=TCISe0_29_V_1) && (xpc10==168/*168:bashint*/)) $display("Processing ACK"); if ((1>=TCISe0_31_V_1) && (xpc10==175/*175:bashint*/)) $display("Processing ACK"); case (xpc10) 0/*0:bashint*/: begin i2c_scl_openable <= 1; i2c_sda_openable <= 1; i2c_sda_out <= 1'd1; i2c_scl_out <= 1; done <= 0; xpc10 <= 1/*1:xpc10:1*/; end 1/*1:bashint*/: begin i2c_sda_out <= 0; xpc10 <= 2/*2:xpc10:2*/; end 2/*2:bashint*/: begin i2c_sda_out <= i2c_sda_out || !checker && i2c_sda_out; i2c_scl_out <= 0; xpc10 <= 3/*3:xpc10:3*/; end 3/*3:bashint*/: begin TCISe0_22_V_0 <= 118; TCISe0_22_V_1 <= 7; i2c_sda_out <= 1'd1; i2c_scl_out <= 0; xpc10 <= 4/*4:xpc10:4*/; end 4/*4:bashint*/: begin i2c_sda_out <= i2c_sda_out || !checker && i2c_sda_out; i2c_scl_out <= 1; xpc10 <= 5/*5:xpc10:5*/; end 5/*5:bashint*/: begin TCISe0_22_V_0 <= (TCISe0_22_V_0<<1); i2c_sda_out <= i2c_sda_out || !checker && i2c_sda_out; i2c_scl_out <= 0; xpc10 <= 6/*6:xpc10:6*/; end 6/*6:bashint*/: begin TCISe0_22_V_1 <= -1+TCISe0_22_V_1; i2c_sda_out <= (0!=(64&TCISe0_22_V_0)) && (1=TCISe0_29_V_1) || !checker && (0!=(128&TCISe0_29_V_0 )) && (1=TCISe0_29_V_1); i2c_scl_out <= ((1=TCISe0_31_V_1) || (0!=(128&TCISe0_31_V_0)) && (1=TCISe0_31_V_1 ) || !checker && (0!=(128&TCISe0_31_V_0)) && (1=TCISe0_29_V_1) || !checker && (0!=(128&TCISe0_29_V_0 )) && (1=TCISe0_29_V_1); i2c_scl_out <= ((1=TCISe0_31_V_1) || (0!=(128&TCISe0_31_V_0)) && (1=TCISe0_31_V_1 ) || !checker && (0!=(128&TCISe0_31_V_0)) && (1=TCISe0_29_V_1) || !checker && (0!=(128&TCISe0_29_V_0 )) && (1=TCISe0_29_V_1); i2c_scl_out <= ((1=TCISe0_31_V_1) || (0!=(128&TCISe0_31_V_0)) && (1=TCISe0_31_V_1 ) || !checker && (0!=(128&TCISe0_31_V_0)) && (1=TCISe0_29_V_1) || !checker && (0!=(128&TCISe0_29_V_0 )) && (1=TCISe0_29_V_1); i2c_scl_out <= ((1=TCISe0_31_V_1) || (0!=(128&TCISe0_31_V_0)) && (1=TCISe0_31_V_1 ) || !checker && (0!=(128&TCISe0_31_V_0)) && (1=TCISe0_29_V_1) || !checker && (0!=(128&TCISe0_29_V_0 )) && (1=TCISe0_29_V_1); i2c_scl_out <= ((1=TCISe0_31_V_1) || (0!=(128&TCISe0_31_V_0)) && (1=TCISe0_31_V_1 ) || !checker && (0!=(128&TCISe0_31_V_0)) && (1=TCISe0_29_V_1) || (0!=(128&TCISe0_29_V_0)) && (1=TCISe0_29_V_1 ) || !checker && (0!=(128&TCISe0_29_V_0)) && (1=TCISe0_31_V_1) || !checker && (0!=(128&TCISe0_31_V_0 )) && (1=TCISe0_31_V_1); i2c_scl_out <= ((1