// CBG Kiwic (Orangepath HPRLS) System
// Verilog output file generated at Fri Feb 29 12:32:00 GMT 2008

// Kiwic: HPR Orange IL/.net front end: Version alpha 10 : 29-Feb-08

// -root test2;test2.Main -vnl VNL.v -sim-rtl 100 


module VNL(clk, reset);
input clk;
  input reset;
  reg hpr_testandset_res212;
  reg hpr_testandset_res211;
  reg hpr_testandset_res208;
  reg hpr_testandset_res207;
  reg pcnet214p;
  reg pcnet210p;
  integer test2_Main_V_0;
  integer test2_Main_V_1;
  reg nel_1____Kiwi_channel_1_empty;
  integer psule____Capsule_foo;
  integer test2_limit;
  reg nel_1_mutex;
  reg psule____Capsule_newlinef;
  integer test2_limit;
   always @(posedge clk) begin 
          case (pcnet214p)
          
          0
           :  begin if (reset) pcnet214p <= 0;
                 if (!reset && nel_1____Kiwi_channel_1_empty) pcnet214p <= 1;
                 if (!reset && !nel_1____Kiwi_channel_1_empty && !psule____Capsule_newlinef) pcnet214p <= 1;
                 if (!reset && !nel_1____Kiwi_channel_1_empty && psule____Capsule_newlinef) pcnet214p <= 1;
                 if (nel_1____Kiwi_channel_1_empty) hpr_testandset_res211 <= 0;
                 if (nel_1____Kiwi_channel_1_empty) nel_1_mutex <= 0;
                 if (!psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) nel_1____Kiwi_channel_1_empty <= 1;
                 if (!psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) hpr_testandset_res211 <= 0;
                 if (!psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) nel_1_mutex <= 0;
                 if (psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) nel_1____Kiwi_channel_1_empty <= 1;
                 if (psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) hpr_testandset_res211 <= 0;
                 if (psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) nel_1_mutex <= 0;
                 if (!nel_1____Kiwi_channel_1_empty) $write("%d ", psule____Capsule_foo);
                 
                 if (psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) $display("");
                 
                 
                  end 
          1
           :  begin if (reset) pcnet214p <= 0;
                 if (nel_1____Kiwi_channel_1_empty) hpr_testandset_res212 <= 0;
                 if (nel_1____Kiwi_channel_1_empty) nel_1_mutex <= 0;
                 if (!psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) hpr_testandset_res212 <= 0;
                 if (!psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) nel_1____Kiwi_channel_1_empty <= 1;
                 if (!psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) hpr_testandset_res211 <= 0;
                 if (!psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) nel_1_mutex <= 0;
                 if (psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) hpr_testandset_res212 <= 0;
                 if (psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) nel_1____Kiwi_channel_1_empty <= 1;
                 if (psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) hpr_testandset_res211 <= 0;
                 if (psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) nel_1_mutex <= 0;
                 if (!nel_1____Kiwi_channel_1_empty) $write("%d ", psule____Capsule_foo);
                 
                 if (psule____Capsule_newlinef && !nel_1____Kiwi_channel_1_empty) $display("");
                 
                 
                  end endcase
          
          case (pcnet210p)
          
          0
           :  begin if (reset) pcnet210p <= 0;
                 if (!reset) pcnet210p <= 1;
                 test2_Main_V_0 <= 1;
                 nel_1____Kiwi_channel_1_empty <= 0;
                 test2_Main_V_1 <= 2;
                 psule____Capsule_foo <= 2;
                 psule____Capsule_newlinef <= 0;
                 hpr_testandset_res207 <= 0;
                 nel_1_mutex <= 0;
                 $display("%s%d", "Times Table Up To ", 5);
                 
                 
                  end 
          1
           :  begin if (reset) pcnet210p <= 0;
                 if (!nel_1____Kiwi_channel_1_empty) hpr_testandset_res208 <= 0;
                 if (!nel_1____Kiwi_channel_1_empty) nel_1_mutex <= 0;
                 if (test2_Main_V_1<5 && nel_1____Kiwi_channel_1_empty) hpr_testandset_res208 <= 0;
                 if (test2_Main_V_1<5 && nel_1____Kiwi_channel_1_empty) nel_1____Kiwi_channel_1_empty <= 0;
                 if (test2_Main_V_1<5 && nel_1____Kiwi_channel_1_empty) test2_Main_V_1 <= test2_Main_V_1+1;
                 if (test2_Main_V_1<5 && nel_1____Kiwi_channel_1_empty) psule____Capsule_foo <= test2_Main_V_0*(test2_Main_V_1+1);
                 if (test2_Main_V_1<5 && nel_1____Kiwi_channel_1_empty) psule____Capsule_newlinef <= test2_Main_V_1+1==4;
                 if (test2_Main_V_1<5 && nel_1____Kiwi_channel_1_empty) hpr_testandset_res207 <= 0;
                 if (test2_Main_V_1<5 && nel_1____Kiwi_channel_1_empty) nel_1_mutex <= 0;
                 if (test2_Main_V_0<5 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) hpr_testandset_res208 <= 0;
                 if (test2_Main_V_0<5 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) nel_1____Kiwi_channel_1_empty <= 0;
                 if (test2_Main_V_0<5 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) test2_Main_V_0 <= test2_Main_V_0+1;
                 if (test2_Main_V_0<5 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) test2_Main_V_1 <= 1;
                 if (test2_Main_V_0<5 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) psule____Capsule_foo <= (test2_Main_V_0+1)*1;
                 if (test2_Main_V_0<5 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) psule____Capsule_newlinef <= 0;
                 if (test2_Main_V_0<5 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) hpr_testandset_res207 <= 0;
                 if (test2_Main_V_0<5 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) nel_1_mutex <= 0;
                 if (4<test2_Main_V_0 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) hpr_testandset_res208 <= 0;
                 if (4<test2_Main_V_0 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) nel_1____Kiwi_channel_1_empty <= 0;
                 if (4<test2_Main_V_0 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) nel_1_mutex <= 0;
                 if (4<test2_Main_V_0 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) test2_Main_V_1 <= test2_Main_V_1+1;
                 if (4<test2_Main_V_0 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) test2_Main_V_0 <= test2_Main_V_0+1;
                 if (4<test2_Main_V_0 && 4<test2_Main_V_1 && nel_1____Kiwi_channel_1_empty) $finish(0);
                 
                 
                  end endcase
           end 
          endmodule