// // $Id: $ // // primesys.v : test wrapper and BVCI ssram xtor for the primes.vnl test. module SIMSYS(); reg reset; reg clk; parameter dwidth = 32; wire [31:0] primes_count; reg [31:0] primes_vol; reg [dwidth-1:0] PA_rdata; reg PA_rerror; reg PA_reop; wire PA_rspack; reg PA_rspval; wire [dwidth/8-1:0] PA_le; wire [31:0] PA_addr; wire [dwidth-1:0] PA_wdata; wire PA_eop; wire [1:0] PA_cmd; wire [6:0] PA_plen; reg PA_cmdack; wire PA_cmdval; reg [31:0] Array [0:10000]; primes iprimes(reset, clk, primes_count, primes_vol, PA_rdata, PA_rerror, PA_reop, PA_rspack, PA_rspval, PA_le, PA_addr, PA_wdata, PA_eop, PA_cmd, PA_plen, PA_cmdval, PA_cmdack); initial clk =0; initial begin reset = 1; # 1000 reset = 0; end always #100 clk = !clk; reg busy; // At most one command in process at a time. reg [7:0] inctr, outctr; reg [31:0] answers [0:255]; always @(posedge clk) if (reset) begin inctr <= 0; busy <= 0; outctr <= 0; PA_cmdack <= 0; end else begin PA_cmdack <= !busy; if (PA_cmdval && PA_cmdack && PA_eop) busy <= 1; if (PA_cmdval && PA_cmdack && PA_cmd == 2) // write command begin Array[PA_addr] <= PA_wdata; $display("ssram write [%d] := %d", PA_addr, PA_wdata); inctr <= inctr + dwidth/8; outctr <= 0; end if (PA_cmdval && PA_cmdack && PA_cmd == 1) // read command begin $display("ssram read [%d] -> %d", PA_addr, Array[PA_addr]); answers[inctr] = Array[PA_addr]; inctr <= inctr + dwidth/8; outctr <= 0; end // Response process if (busy) begin PA_rspval <= 1; PA_rdata = answers[outctr]; outctr <= (outctr+dwidth/8 == inctr) ? 0: outctr+dwidth/8; if (outctr+dwidth/8 == inctr) begin PA_reop <= 1; inctr <= 0; busy <= 0; end end else begin PA_rspval <= 0; PA_reop <= 0; end //if (PA_cmdval) $display("Cmd %d, len=%d, count=%d/%d, addr=%d", PA_cmd, PA_plen, inctr, outctr, PA_addr); $display("Monitor primes_count=%d", primes_count); end initial #100000000 begin $display("Finish, primes_count=%d", primes_count); $finish(); end endmodule // eof