// hpr/ls $Id: hprls_sml_lib.sml,v 1.36 2008/08/13 18:01:50 djg11 Exp $
// -sim 15000 -root PRIMES -sysc primes.cpp -vnl primes.vnl -restructure BVCI -preserve-sequencer 1 


module primes(reset, clk);
input reset;
  input clk;
  reg stall;
  reg [3:0] PA[999:0];
  wire [15:0] k;
  reg [15:0] j;
  reg [15:0] i;
  reg [3:0] nputdesign10pc;
   always @(posedge clk) begin //Start Hpr/ls
          if (reset) nputdesign10pc <= 0;
           else 
          case (nputdesign10pc)
          
          0:  begin nputdesign10pc <= 8;
                 i <= 0;
                 $write("Primes test up to %i, starting now=%i\n", 50, $time);
                 
                 
                  end 
          1: nputdesign10pc <= 8;
          
          2: nputdesign10pc <= 9;
          
          3: nputdesign10pc <= 10;
          
          4: nputdesign10pc <= 12;
          
          5: nputdesign10pc <= 11;
          
          6: nputdesign10pc <= 13;
          
          7: nputdesign10pc <= 14;
          
          8:  begin if (49<=i) 
                   begin nputdesign10pc <= 14;
                      PA[i] <= 1;
                      i <= i+1;
                      j <= 2;
                      
                       end if (i<49) 
                   begin PA[i] <= 1;
                      i <= i+1;
                      
                       end 
                  end 
          9:  begin nputdesign10pc <= 8;
                 i <= 0;
                 $write("\n");
                 
                 $write("Primes test: complete at tnow=%i.\n", $time);
                 
                 $finish(0);
                 
                 $write("Primes test up to %i, starting now=%i\n", 50, $time);
                 
                 
                  end 
          10:  begin if (49<=i) 
                    begin nputdesign10pc <= 9;
                       i <= i+1;
                       
                        end if (!(PA[i+1]) && i<49) i <= i+1;
                  if (!(!(PA[i+1])) && i<49) i <= i+1;
                  if (!(!(PA[i+1])) && i<49) $write("%i ", i+1);
                  
                  
                   end 
          11:  begin if (50<=i && 49<=j) nputdesign10pc <= 12;
                  if (i<50) nputdesign10pc <= 13;
                  if (50<=i && 49<=j) j <= j+1;
                  if (50<=i && j<49) 
                    begin j <= j+1;
                       i <= j+1+j+1;
                       
                        end if (i<50) 
                    begin PA[i] <= 0;
                       i <= i+j;
                       
                        end if (50<=i && 49<=j) $write("The primes are:");
                  
                  
                   end 
          12:  begin if (!(PA[1])) nputdesign10pc <= 10;
                  if (!(!(PA[1]))) nputdesign10pc <= 10;
                  if (!(PA[1])) i <= 1;
                  if (!(!(PA[1]))) i <= 1;
                  if (!(!(PA[1]))) $write("%i ", 1);
                  
                  
                   end 
          13:  begin if (50<=i && 49<=j) nputdesign10pc <= 12;
                  if (50<=i && j<49) nputdesign10pc <= 11;
                  if (50<=i && 49<=j) j <= j+1;
                  if (50<=i && j<49) 
                    begin j <= j+1;
                       i <= j+1+j+1;
                       
                        end if (i<50) 
                    begin PA[i] <= 0;
                       i <= i+j;
                       
                        end if (50<=i && 49<=j) $write("The primes are:");
                  
                  
                   end 
          14:  begin if (50<=j) nputdesign10pc <= 12;
                  if (j<50) 
                    begin nputdesign10pc <= 11;
                       i <= j+j;
                       
                        end $write("Primes test: cleared array at tnow=%i \n", $time);
                  
                  if (50<=j) $write("The primes are:");
                  
                  
                   end endcase
          if (reset) stall <= 0;
           else stall <= 0&!reset;
          //End Hpr/ls


           end 
          // Start delx Input design
  // End delx Input design


  endmodule

// eof (hprls verilog)