// CBG Orangepath HPR L/S System

// Verilog output file generated at 31/05/2016 12:31:22
// Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 2.14 : 29-May-2016 Linux/X86_64:koo
//  Z:\home\djg11\d320\hprls\kiwipro\kiwic\distro\lib\kiwic.exe -vnl-roundtrip=disable -report-each-step -kiwic-finish=enable -kiwic-kcode-dump=enable -kiwic-cil-dump=separately test49.exe -sim 1800 -vnl-rootmodname=DUT -vnl-resets=synchronous -vnl=test49.v -res2-loadstore-port-count=0 -bevelab-default-pause-mode=hard -give-backtrace -report-each-step
`timescale 1ns/1ns


module DUT(input clk, input reset);
function [31:0] hpr_dbl2flt2;
input [63:0] arg;

reg          signi;
reg [10:0]   expi;
reg [51:0]   manti;
reg [7:0]    expo;
reg [22:0]   manto;
reg  overflow, scase_inf, scase_zero, scase_nan, fail;

begin
  { signi, expi, manti } = arg;  // Deconstruct input arg
  scase_zero = (arg[62:0] == 63'd0);
  scase_inf = (expi == 11'h7ff) && (manti == 0);
  scase_nan = (expi == 11'h7ff) && (manti != 0);
// We can report fail on overflow but better to report infinity.
  fail = 0;
  overflow = (expi[10] == expi[9]) ||(expi[10] == expi[8]) ||(expi[10] == expi[7]);
  expo = { expi[10], expi[6:0]};
  manto = manti[51:51-22];
  scase_inf = scase_inf || overflow;
  hpr_dbl2flt2[31]    = signi;
  hpr_dbl2flt2[30:23] = (scase_inf)? 8'hff: (scase_nan)? 8'hff: (scase_zero)? 8'd0: expo;
  hpr_dbl2flt2[22:0]  = (scase_inf)? 23'd0: (scase_nan)? -23'd1: (scase_zero)? 23'd0: manto;
end
endfunction

function [63:0] hpr_flt2dbl1;
input [31:0] darg;
hpr_flt2dbl1 = {darg[31], darg[30], {3{~darg[30]}}, darg[29:23], darg[22:0], {29{1'b0}}};
endfunction

function [63:0] hpr_flt2dbl0;
input [31:0] darg;
hpr_flt2dbl0 = {darg[31], darg[30], {3{~darg[30]}}, darg[29:23], darg[22:0], {29{1'b0}}};
endfunction

  reg signed [31:0] test49_volx;
  integer Ttte0_5_V_0;
  reg [63:0] Ttte0_5_V_1;
  reg [31:0] Ttte0_5_V_2;
  reg [31:0] Ttte0_5_V_3;
  integer Ttte0_5_V_4;
  integer Ttte0_6_V_1;
  reg [63:0] A_FPD_CC_SCALbx10_ARA0[5:0];
  wire [63:0] fpcvt10_result;
  reg signed [31:0] fpcvt10_arg;
  wire fpcvt10_fail;
  wire [63:0] CVFPMULTIPLIER10_FPRR;
  reg [63:0] CVFPMULTIPLIER10_A0;
  reg [63:0] CVFPMULTIPLIER10_A1;
  wire CVFPMULTIPLIER10_fail;
  wire signed [31:0] fpcvt12_result;
  reg [31:0] fpcvt12_arg;
  wire fpcvt12_fail;
  wire [31:0] fpcvt14_result;
  reg signed [31:0] fpcvt14_arg;
  wire fpcvt14_fail;
  wire [31:0] CVFPMULTIPLIER12_FPRR;
  reg [31:0] CVFPMULTIPLIER12_A0;
  reg [31:0] CVFPMULTIPLIER12_A1;
  wire CVFPMULTIPLIER12_fail;
  wire [63:0] fpcvt16_result;
  reg signed [31:0] fpcvt16_arg;
  wire fpcvt16_fail;
  wire [63:0] CVFPMULTIPLIER14_FPRR;
  reg [63:0] CVFPMULTIPLIER14_A0;
  reg [63:0] CVFPMULTIPLIER14_A1;
  wire CVFPMULTIPLIER14_fail;
  wire [63:0] CVFPMULTIPLIER16_FPRR;
  reg [63:0] CVFPMULTIPLIER16_A0;
  reg [63:0] CVFPMULTIPLIER16_A1;
  wire CVFPMULTIPLIER16_fail;
  wire [63:0] CVFPADDER10_FPRR;
  reg [63:0] CVFPADDER10_A0;
  reg [63:0] CVFPADDER10_A1;
  wire CVFPADDER10_fail;
  wire [63:0] CVFPDIVIDER10_FPRR;
  reg [63:0] CVFPDIVIDER10_NN;
  reg [63:0] CVFPDIVIDER10_DD;
  wire CVFPDIVIDER10_fail;
  wire [63:0] CVFPADDER12_FPRR;
  reg [63:0] CVFPADDER12_A0;
  reg [63:0] CVFPADDER12_A1;
  wire CVFPADDER12_fail;
  reg [63:0] CVFPDIVIDER10RRh10hold;
  reg CVFPDIVIDER10RRh10shot0;
  reg CVFPDIVIDER10RRh10shot1;
  reg CVFPDIVIDER10RRh10shot2;
  reg CVFPDIVIDER10RRh10shot3;
  reg CVFPDIVIDER10RRh10shot4;
  reg [63:0] CVFPADDER12RRh10hold;
  reg CVFPADDER12RRh10shot0;
  reg CVFPADDER12RRh10shot1;
  reg CVFPADDER12RRh10shot2;
  reg CVFPADDER12RRh10shot3;
  reg [63:0] CVFPADDER10RRh10hold;
  reg CVFPADDER10RRh10shot0;
  reg CVFPADDER10RRh10shot1;
  reg CVFPADDER10RRh10shot2;
  reg CVFPADDER10RRh10shot3;
  reg [63:0] CVFPMULTIPLIER16RRh10hold;
  reg CVFPMULTIPLIER16RRh10shot0;
  reg CVFPMULTIPLIER16RRh10shot1;
  reg CVFPMULTIPLIER16RRh10shot2;
  reg [63:0] CVFPMULTIPLIER14RRh10hold;
  reg CVFPMULTIPLIER14RRh10shot0;
  reg CVFPMULTIPLIER14RRh10shot1;
  reg CVFPMULTIPLIER14RRh10shot2;
  reg [63:0] fpcvt16RRh10hold;
  reg fpcvt16RRh10shot0;
  reg fpcvt16RRh10shot1;
  reg [31:0] CVFPMULTIPLIER12RRh10hold;
  reg CVFPMULTIPLIER12RRh10shot0;
  reg CVFPMULTIPLIER12RRh10shot1;
  reg CVFPMULTIPLIER12RRh10shot2;
  reg [31:0] fpcvt14RRh10hold;
  reg fpcvt14RRh10shot0;
  reg fpcvt14RRh10shot1;
  reg signed [31:0] fpcvt12RRh10hold;
  reg fpcvt12RRh10shot0;
  reg fpcvt12RRh10shot1;
  reg [63:0] CVFPMULTIPLIER10RRh10hold;
  reg CVFPMULTIPLIER10RRh10shot0;
  reg CVFPMULTIPLIER10RRh10shot1;
  reg CVFPMULTIPLIER10RRh10shot2;
  reg [63:0] fpcvt10RRh10hold;
  reg fpcvt10RRh10shot0;
  reg fpcvt10RRh10shot1;
  reg [4:0] xpc10nz;
 always   @(* )  begin 
       CVFPDIVIDER10_NN = 0;
       CVFPDIVIDER10_DD = 0;
       CVFPADDER12_A0 = 0;
       CVFPADDER12_A1 = 0;
       CVFPADDER10_A0 = 0;
       CVFPADDER10_A1 = 0;
       CVFPMULTIPLIER16_A0 = 0;
       CVFPMULTIPLIER16_A1 = 0;
       CVFPMULTIPLIER14_A0 = 0;
       CVFPMULTIPLIER14_A1 = 0;
       fpcvt16_arg = 0;
       CVFPMULTIPLIER12_A0 = 0;
       CVFPMULTIPLIER12_A1 = 0;
       fpcvt14_arg = 0;
       fpcvt12_arg = 0;
       CVFPMULTIPLIER10_A0 = 0;
       CVFPMULTIPLIER10_A1 = 0;
       fpcvt10_arg = 0;
      if ((xpc10nz==1'd1/*US*/))  fpcvt10_arg = test49_volx;
          
      case (xpc10nz)
          2'd3/*US*/:  begin 
               CVFPMULTIPLIER10_A1 = 64'h_40aa_0466_6666_6666;
               CVFPMULTIPLIER10_A0 = ((xpc10nz==2'd3/*US*/)? fpcvt10_result: fpcvt10RRh10hold);
               end 
              
          4'd8/*US*/:  begin 
               fpcvt12_arg = Ttte0_5_V_2;
               fpcvt14_arg = Ttte0_5_V_0;
               end 
              
          4'd10/*US*/:  begin 
               CVFPMULTIPLIER12_A1 = ((xpc10nz==4'd10/*US*/)? fpcvt14_result: fpcvt14RRh10hold);
               CVFPMULTIPLIER12_A0 = 32'h_40e3_f34d;
               end 
              endcase
      if ((Ttte0_5_V_0<3'd5))  begin 
              if ((xpc10nz==4'd15/*US*/))  fpcvt16_arg = 32'd1+test49_volx+Ttte0_5_V_0;
                  if ((xpc10nz==5'd17/*US*/))  begin 
                       CVFPMULTIPLIER14_A1 = ((xpc10nz==5'd17/*US*/)? fpcvt16_result: fpcvt16RRh10hold);
                       CVFPMULTIPLIER14_A0 = 64'h_40aa_0466_6666_6666;
                       end 
                       end 
              if ((xpc10nz==5'd22/*US*/))  begin 
               CVFPMULTIPLIER16_A1 = A_FPD_CC_SCALbx10_ARA0[1'd1];
               CVFPMULTIPLIER16_A0 = 64'h_4059_0000_0000_0000;
               CVFPADDER10_A1 = A_FPD_CC_SCALbx10_ARA0[2'd2];
               CVFPADDER10_A0 = 64'h_c059_0000_0000_0000;
               CVFPADDER12_A1 = A_FPD_CC_SCALbx10_ARA0[3'd4];
               CVFPADDER12_A0 = 64'h_4059_0000_0000_0000;
               CVFPDIVIDER10_DD = 64'h_4059_0000_0000_0000;
               CVFPDIVIDER10_NN = A_FPD_CC_SCALbx10_ARA0[2'd3];
               end 
               end 
      

 always   @(posedge clk )  begin 
      //Start structure HPR test49.exe
      if (reset)  begin 
               Ttte0_6_V_1 <= 32'd0;
               Ttte0_5_V_3 <= 32'd0;
               Ttte0_5_V_4 <= 32'd0;
               Ttte0_5_V_2 <= 32'd0;
               Ttte0_5_V_0 <= 32'd0;
               Ttte0_5_V_1 <= 64'd0;
               test49_volx <= 32'd0;
               fpcvt10RRh10hold <= 64'd0;
               fpcvt10RRh10shot1 <= 1'd0;
               CVFPMULTIPLIER10RRh10hold <= 64'd0;
               CVFPMULTIPLIER10RRh10shot1 <= 1'd0;
               CVFPMULTIPLIER10RRh10shot2 <= 1'd0;
               fpcvt12RRh10hold <= 32'd0;
               fpcvt12RRh10shot1 <= 1'd0;
               fpcvt14RRh10hold <= 32'd0;
               fpcvt14RRh10shot1 <= 1'd0;
               CVFPMULTIPLIER12RRh10hold <= 32'd0;
               CVFPMULTIPLIER12RRh10shot1 <= 1'd0;
               CVFPMULTIPLIER12RRh10shot2 <= 1'd0;
               fpcvt16RRh10hold <= 64'd0;
               fpcvt16RRh10shot1 <= 1'd0;
               CVFPMULTIPLIER14RRh10hold <= 64'd0;
               CVFPMULTIPLIER14RRh10shot1 <= 1'd0;
               CVFPMULTIPLIER14RRh10shot2 <= 1'd0;
               CVFPMULTIPLIER16RRh10hold <= 64'd0;
               CVFPMULTIPLIER16RRh10shot1 <= 1'd0;
               CVFPMULTIPLIER16RRh10shot2 <= 1'd0;
               CVFPADDER10RRh10hold <= 64'd0;
               CVFPADDER10RRh10shot1 <= 1'd0;
               CVFPADDER10RRh10shot2 <= 1'd0;
               CVFPADDER10RRh10shot3 <= 1'd0;
               CVFPADDER12RRh10hold <= 64'd0;
               CVFPADDER12RRh10shot1 <= 1'd0;
               CVFPADDER12RRh10shot2 <= 1'd0;
               CVFPADDER12RRh10shot3 <= 1'd0;
               CVFPDIVIDER10RRh10hold <= 64'd0;
               CVFPDIVIDER10RRh10shot1 <= 1'd0;
               CVFPDIVIDER10RRh10shot2 <= 1'd0;
               CVFPDIVIDER10RRh10shot3 <= 1'd0;
               CVFPDIVIDER10RRh10shot4 <= 1'd0;
               CVFPDIVIDER10RRh10shot0 <= 1'd0;
               CVFPADDER12RRh10shot0 <= 1'd0;
               CVFPADDER10RRh10shot0 <= 1'd0;
               CVFPMULTIPLIER16RRh10shot0 <= 1'd0;
               CVFPMULTIPLIER14RRh10shot0 <= 1'd0;
               fpcvt16RRh10shot0 <= 1'd0;
               CVFPMULTIPLIER12RRh10shot0 <= 1'd0;
               fpcvt14RRh10shot0 <= 1'd0;
               fpcvt12RRh10shot0 <= 1'd0;
               CVFPMULTIPLIER10RRh10shot0 <= 1'd0;
               fpcvt10RRh10shot0 <= 1'd0;
               xpc10nz <= 5'd0;
               end 
               else  begin 
              if ((xpc10nz==5'd27/*US*/)) if ((Ttte0_6_V_1>=2'd2))  begin 
                          $display("phase1: data %1d  is %F", 0, $bitstoreal(A_FPD_CC_SCALbx10_ARA0[0]));
                          $display("phase1: data %1d  is %F", 1'd1, $bitstoreal(((xpc10nz==5'd25/*US*/)? CVFPMULTIPLIER16_FPRR: CVFPMULTIPLIER16RRh10hold
                          )));
                          $display("phase1: data %1d  is %F", 2'd2, $bitstoreal(((xpc10nz==5'd26/*US*/)? CVFPADDER10_FPRR: CVFPADDER10RRh10hold
                          )));
                          $display("phase1: data %1d  is %F", 2'd3, $bitstoreal(((xpc10nz==5'd27/*US*/)? CVFPDIVIDER10_FPRR: CVFPDIVIDER10RRh10hold
                          )));
                          $display("phase1: data %1d  is %F", 3'd4, $bitstoreal(((xpc10nz==5'd26/*US*/)? CVFPADDER12_FPRR: CVFPADDER12RRh10hold
                          )));
                          $display("phase1: data %1d  is %F", 3'd5, $bitstoreal(A_FPD_CC_SCALbx10_ARA0[3'd5]));
                          $display("Kiwi Demo - Test49 phase1 finished.");
                          $display("Test49 done.");
                          $finish(0);
                           end 
                           else  begin 
                          $display("phase1: data %1d  is %F", 0, $bitstoreal(A_FPD_CC_SCALbx10_ARA0[0]));
                          $display("phase1: data %1d  is %F", 1'd1, $bitstoreal(((xpc10nz==5'd25/*US*/)? CVFPMULTIPLIER16_FPRR: CVFPMULTIPLIER16RRh10hold
                          )));
                          $display("phase1: data %1d  is %F", 2'd2, $bitstoreal(((xpc10nz==5'd26/*US*/)? CVFPADDER10_FPRR: CVFPADDER10RRh10hold
                          )));
                          $display("phase1: data %1d  is %F", 2'd3, $bitstoreal(((xpc10nz==5'd27/*US*/)? CVFPDIVIDER10_FPRR: CVFPDIVIDER10RRh10hold
                          )));
                          $display("phase1: data %1d  is %F", 3'd4, $bitstoreal(((xpc10nz==5'd26/*US*/)? CVFPADDER12_FPRR: CVFPADDER12RRh10hold
                          )));
                          $display("phase1: data %1d  is %F", 3'd5, $bitstoreal(A_FPD_CC_SCALbx10_ARA0[3'd5]));
                           end 
                          if ((Ttte0_5_V_0>=3'd5) && (xpc10nz==4'd15/*US*/)) $display("Kiwi Demo - Test49 phase1 starting.");
                  
              case (xpc10nz)
                  0/*US*/: $display("Kiwi Demo - Test49 starting.");

                  3'd6/*US*/: $display("Kiwi Demo - Test49 phase0 starting.");

                  3'd7/*US*/: $display("data %1d  qfp0=%F", Ttte0_5_V_0, $bitstoreal(Ttte0_5_V_1));

                  4'd14/*US*/: $display("                  qfp1=%F  qfp2=%F  qfp3=%1d", $bitstoreal(hpr_flt2dbl0(Ttte0_5_V_2)), $bitstoreal(hpr_flt2dbl1(Ttte0_5_V_3
                  )), Ttte0_5_V_4);

                  5'd21/*US*/:  begin 
                       Ttte0_6_V_1 <= 32'd0;
                       A_FPD_CC_SCALbx10_ARA0[3'd5] <= 64'h_4005_ae14_7ae1_47ae;
                       A_FPD_CC_SCALbx10_ARA0[3'd4] <= 64'h_4009_21ca_c083_126f;
                       A_FPD_CC_SCALbx10_ARA0[2'd3] <= 64'h_4009_21ca_c083_126f;
                       A_FPD_CC_SCALbx10_ARA0[2'd2] <= 64'h_4009_21ca_c083_126f;
                       A_FPD_CC_SCALbx10_ARA0[1'd1] <= 64'h_4009_21ca_c083_126f;
                       A_FPD_CC_SCALbx10_ARA0[0] <= 64'h_4009_21ca_c083_126f;
                       xpc10nz <= 5'd22/*xpc10nz*/;
                       end 
                      
                  5'd27/*US*/:  begin 
                       A_FPD_CC_SCALbx10_ARA0[3'd4] <= ((xpc10nz==5'd26/*US*/)? CVFPADDER12_FPRR: CVFPADDER12RRh10hold);
                       A_FPD_CC_SCALbx10_ARA0[2'd3] <= ((xpc10nz==5'd27/*US*/)? CVFPDIVIDER10_FPRR: CVFPDIVIDER10RRh10hold);
                       A_FPD_CC_SCALbx10_ARA0[2'd2] <= ((xpc10nz==5'd26/*US*/)? CVFPADDER10_FPRR: CVFPADDER10RRh10hold);
                       A_FPD_CC_SCALbx10_ARA0[1'd1] <= ((xpc10nz==5'd25/*US*/)? CVFPMULTIPLIER16_FPRR: CVFPMULTIPLIER16RRh10hold);
                       Ttte0_6_V_1 <= 32'd1+Ttte0_6_V_1;
                       xpc10nz <= 5'd22/*xpc10nz*/;
                       end 
                      endcase
              if ((Ttte0_5_V_0<3'd5)) 
                  case (xpc10nz)
                      4'd15/*US*/:  xpc10nz <= 5'd16/*xpc10nz*/;

                      5'd20/*US*/:  begin 
                           Ttte0_5_V_0 <= 32'd1+Ttte0_5_V_0;
                           Ttte0_5_V_1 <= ((xpc10nz==5'd20/*US*/)? CVFPMULTIPLIER14_FPRR: CVFPMULTIPLIER14RRh10hold);
                           end 
                          endcase
                   else if ((xpc10nz==4'd15/*US*/))  begin 
                           Ttte0_5_V_0 <= 32'd1+Ttte0_5_V_0;
                           xpc10nz <= 5'd21/*xpc10nz*/;
                           end 
                          
              case (xpc10nz)
                  0/*US*/:  begin 
                       test49_volx <= 32'd100;
                       xpc10nz <= 1'd1/*xpc10nz*/;
                       end 
                      
                  3'd6/*US*/:  begin 
                       Ttte0_5_V_0 <= 32'd0;
                       Ttte0_5_V_1 <= ((xpc10nz==3'd6/*US*/)? CVFPMULTIPLIER10_FPRR: CVFPMULTIPLIER10RRh10hold);
                       xpc10nz <= 3'd7/*xpc10nz*/;
                       end 
                      
                  3'd7/*US*/:  begin 
                       Ttte0_5_V_2 <= hpr_dbl2flt2(Ttte0_5_V_1);
                       xpc10nz <= 4'd8/*xpc10nz*/;
                       end 
                      
                  4'd13/*US*/:  begin 
                       Ttte0_5_V_3 <= ((xpc10nz==4'd13/*US*/)? CVFPMULTIPLIER12_FPRR: CVFPMULTIPLIER12RRh10hold);
                       Ttte0_5_V_4 <= ((xpc10nz==4'd10/*US*/)? fpcvt12_result: fpcvt12RRh10hold);
                       xpc10nz <= 4'd14/*xpc10nz*/;
                       end 
                      
                  4'd14/*US*/:  xpc10nz <= 4'd15/*xpc10nz*/;

                  5'd20/*US*/:  xpc10nz <= 3'd7/*xpc10nz*/;
              endcase
              if (fpcvt10RRh10shot1)  fpcvt10RRh10hold <= fpcvt10_result;
                   fpcvt10RRh10shot1 <= fpcvt10RRh10shot0;
              if (CVFPMULTIPLIER10RRh10shot2)  CVFPMULTIPLIER10RRh10hold <= CVFPMULTIPLIER10_FPRR;
                   CVFPMULTIPLIER10RRh10shot1 <= CVFPMULTIPLIER10RRh10shot0;
               CVFPMULTIPLIER10RRh10shot2 <= CVFPMULTIPLIER10RRh10shot1;
              if (fpcvt12RRh10shot1)  fpcvt12RRh10hold <= fpcvt12_result;
                   fpcvt12RRh10shot1 <= fpcvt12RRh10shot0;
              if (fpcvt14RRh10shot1)  fpcvt14RRh10hold <= fpcvt14_result;
                   fpcvt14RRh10shot1 <= fpcvt14RRh10shot0;
              if (CVFPMULTIPLIER12RRh10shot2)  CVFPMULTIPLIER12RRh10hold <= CVFPMULTIPLIER12_FPRR;
                   CVFPMULTIPLIER12RRh10shot1 <= CVFPMULTIPLIER12RRh10shot0;
               CVFPMULTIPLIER12RRh10shot2 <= CVFPMULTIPLIER12RRh10shot1;
              if (fpcvt16RRh10shot1)  fpcvt16RRh10hold <= fpcvt16_result;
                   fpcvt16RRh10shot1 <= fpcvt16RRh10shot0;
              if (CVFPMULTIPLIER14RRh10shot2)  CVFPMULTIPLIER14RRh10hold <= CVFPMULTIPLIER14_FPRR;
                   CVFPMULTIPLIER14RRh10shot1 <= CVFPMULTIPLIER14RRh10shot0;
               CVFPMULTIPLIER14RRh10shot2 <= CVFPMULTIPLIER14RRh10shot1;
              if (CVFPMULTIPLIER16RRh10shot2)  CVFPMULTIPLIER16RRh10hold <= CVFPMULTIPLIER16_FPRR;
                   CVFPMULTIPLIER16RRh10shot1 <= CVFPMULTIPLIER16RRh10shot0;
               CVFPMULTIPLIER16RRh10shot2 <= CVFPMULTIPLIER16RRh10shot1;
              if (CVFPADDER10RRh10shot3)  CVFPADDER10RRh10hold <= CVFPADDER10_FPRR;
                   CVFPADDER10RRh10shot1 <= CVFPADDER10RRh10shot0;
               CVFPADDER10RRh10shot2 <= CVFPADDER10RRh10shot1;
               CVFPADDER10RRh10shot3 <= CVFPADDER10RRh10shot2;
              if (CVFPADDER12RRh10shot3)  CVFPADDER12RRh10hold <= CVFPADDER12_FPRR;
                   CVFPADDER12RRh10shot1 <= CVFPADDER12RRh10shot0;
               CVFPADDER12RRh10shot2 <= CVFPADDER12RRh10shot1;
               CVFPADDER12RRh10shot3 <= CVFPADDER12RRh10shot2;
              if (CVFPDIVIDER10RRh10shot4)  CVFPDIVIDER10RRh10hold <= CVFPDIVIDER10_FPRR;
                   CVFPDIVIDER10RRh10shot1 <= CVFPDIVIDER10RRh10shot0;
               CVFPDIVIDER10RRh10shot2 <= CVFPDIVIDER10RRh10shot1;
               CVFPDIVIDER10RRh10shot3 <= CVFPDIVIDER10RRh10shot2;
               CVFPDIVIDER10RRh10shot4 <= CVFPDIVIDER10RRh10shot3;
               CVFPDIVIDER10RRh10shot0 <= (xpc10nz==5'd22/*US*/);
               CVFPADDER12RRh10shot0 <= (xpc10nz==5'd22/*US*/);
               CVFPADDER10RRh10shot0 <= (xpc10nz==5'd22/*US*/);
               CVFPMULTIPLIER16RRh10shot0 <= (xpc10nz==5'd22/*US*/);
               CVFPMULTIPLIER14RRh10shot0 <= (Ttte0_5_V_0<3'd5) && (xpc10nz==5'd17/*US*/);
               fpcvt16RRh10shot0 <= (Ttte0_5_V_0<3'd5) && (xpc10nz==4'd15/*US*/);
               CVFPMULTIPLIER12RRh10shot0 <= (xpc10nz==4'd10/*US*/);
               fpcvt14RRh10shot0 <= (xpc10nz==4'd8/*US*/);
               fpcvt12RRh10shot0 <= (xpc10nz==4'd8/*US*/);
               CVFPMULTIPLIER10RRh10shot0 <= (xpc10nz==2'd3/*US*/);
               fpcvt10RRh10shot0 <= (xpc10nz==1'd1/*US*/);
              if ((xpc10nz==1'd1/*US*/))  xpc10nz <= 2'd2/*xpc10nz*/;
                  if ((xpc10nz==2'd2/*US*/))  xpc10nz <= 2'd3/*xpc10nz*/;
                  if ((xpc10nz==2'd3/*US*/))  xpc10nz <= 3'd4/*xpc10nz*/;
                  if ((xpc10nz==3'd4/*US*/))  xpc10nz <= 3'd5/*xpc10nz*/;
                  if ((xpc10nz==3'd5/*US*/))  xpc10nz <= 3'd6/*xpc10nz*/;
                  if ((xpc10nz==4'd8/*US*/))  xpc10nz <= 4'd9/*xpc10nz*/;
                  if ((xpc10nz==4'd9/*US*/))  xpc10nz <= 4'd10/*xpc10nz*/;
                  if ((xpc10nz==4'd10/*US*/))  xpc10nz <= 4'd11/*xpc10nz*/;
                  if ((xpc10nz==4'd11/*US*/))  xpc10nz <= 4'd12/*xpc10nz*/;
                  if ((xpc10nz==4'd12/*US*/))  xpc10nz <= 4'd13/*xpc10nz*/;
                  if ((xpc10nz==5'd16/*US*/))  xpc10nz <= 5'd17/*xpc10nz*/;
                  if ((xpc10nz==5'd17/*US*/))  xpc10nz <= 5'd18/*xpc10nz*/;
                  if ((xpc10nz==5'd18/*US*/))  xpc10nz <= 5'd19/*xpc10nz*/;
                  if ((xpc10nz==5'd19/*US*/))  xpc10nz <= 5'd20/*xpc10nz*/;
                  if ((xpc10nz==5'd22/*US*/))  xpc10nz <= 5'd23/*xpc10nz*/;
                  if ((xpc10nz==5'd23/*US*/))  xpc10nz <= 5'd24/*xpc10nz*/;
                  if ((xpc10nz==5'd24/*US*/))  xpc10nz <= 5'd25/*xpc10nz*/;
                  if ((xpc10nz==5'd25/*US*/))  xpc10nz <= 5'd26/*xpc10nz*/;
                  if ((xpc10nz==5'd26/*US*/))  xpc10nz <= 5'd27/*xpc10nz*/;
                   end 
              //End structure HPR test49.exe


       end 
      

  CV_FP_CVT_FL2_F64_I32 ifpcvt10(clk, fpcvt10_result, fpcvt10_arg, fpcvt10_fail);
  CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER10(clk, reset, CVFPMULTIPLIER10_FPRR, CVFPMULTIPLIER10_A0, CVFPMULTIPLIER10_A1, CVFPMULTIPLIER10_fail
);
  CV_FP_CVT_FL2_I32_F32 ifpcvt12(clk, fpcvt12_result, fpcvt12_arg, fpcvt12_fail);
  CV_FP_CVT_FL2_F32_I32 ifpcvt14(clk, fpcvt14_result, fpcvt14_arg, fpcvt14_fail);
  CV_FP_FL3_SP_MULTIPLIER CVFPMULTIPLIER12(clk, reset, CVFPMULTIPLIER12_FPRR, CVFPMULTIPLIER12_A0, CVFPMULTIPLIER12_A1, CVFPMULTIPLIER12_fail
);
  CV_FP_CVT_FL2_F64_I32 ifpcvt16(clk, fpcvt16_result, fpcvt16_arg, fpcvt16_fail);
  CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER14(clk, reset, CVFPMULTIPLIER14_FPRR, CVFPMULTIPLIER14_A0, CVFPMULTIPLIER14_A1, CVFPMULTIPLIER14_fail
);
  CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER16(clk, reset, CVFPMULTIPLIER16_FPRR, CVFPMULTIPLIER16_A0, CVFPMULTIPLIER16_A1, CVFPMULTIPLIER16_fail
);
  CV_FP_FL4_DP_ADDER CVFPADDER10(clk, reset, CVFPADDER10_FPRR, CVFPADDER10_A0, CVFPADDER10_A1, CVFPADDER10_fail);
  CV_FP_FL5_DP_DIVIDER CVFPDIVIDER10(clk, reset, CVFPDIVIDER10_FPRR, CVFPDIVIDER10_NN, CVFPDIVIDER10_DD, CVFPDIVIDER10_fail);
  CV_FP_FL4_DP_ADDER CVFPADDER12(clk, reset, CVFPADDER12_FPRR, CVFPADDER12_A0, CVFPADDER12_A1, CVFPADDER12_fail);
// 1 vectors of width 5
// 33 vectors of width 1
// 21 vectors of width 64
// 12 vectors of width 32
// 6 array locations of width 64
// 96 bits in scalar variables
// Total state bits in module = 2246 bits.
// 619 continuously assigned (wire/non-state) bits 
//   cell CV_FP_CVT_FL2_F64_I32 count=2
//   cell CV_FP_FL3_DP_MULTIPLIER count=3
//   cell CV_FP_CVT_FL2_I32_F32 count=1
//   cell CV_FP_CVT_FL2_F32_I32 count=1
//   cell CV_FP_FL3_SP_MULTIPLIER count=1
//   cell CV_FP_FL4_DP_ADDER count=2
//   cell CV_FP_FL5_DP_DIVIDER count=1
// Total number of leaf cells = 11
endmodule

//  
// LCP delay estimations included: turn off with -vnl-lcp-delay-estimate=disable
//HPR L/S (orangepath) auxiliary reports.
//KiwiC compilation report
//Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 2.14 : 29-May-2016
//31/05/2016 12:31:15
//Cmd line args:  Z:\home\djg11\d320\hprls\kiwipro\kiwic\distro\lib\kiwic.exe -vnl-roundtrip=disable -report-each-step -kiwic-finish=enable -kiwic-kcode-dump=enable -kiwic-cil-dump=separately test49.exe -sim 1800 -vnl-rootmodname=DUT -vnl-resets=synchronous -vnl=test49.v -res2-loadstore-port-count=0 -bevelab-default-pause-mode=hard -give-backtrace -report-each-step


//----------------------------------------------------------

//Report from KiwiC-fe.rpt:::
//KiwiC: front end input processing of class or method called KiwiSystem/Kiwi
//
//root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor10
//
//KiwiC start_thread (or entry point) id=cctor10
//
//Root method elaborated: specificf=S_kickoff_collate leftover=1+0
//
//KiwiC: front end input processing of class or method called System/BitConverter
//
//root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor12
//
//KiwiC start_thread (or entry point) id=cctor12
//
//Root method elaborated: specificf=S_kickoff_collate leftover=1+1
//
//KiwiC: front end input processing of class or method called test49
//
//root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor14
//
//KiwiC start_thread (or entry point) id=cctor14
//
//Root method elaborated: specificf=S_kickoff_collate leftover=1+2
//
//KiwiC: front end input processing of class or method called test49
//
//root_compiler: start elaborating class 'test49'
//
//elaborating class 'test49'
//
//compiling static method as entry point: style=Root idl=test49/Main
//
//Performing root elaboration of method Main
//
//KiwiC start_thread (or entry point) id=Main10
//
//root_compiler class done: test49
//
//Report of all settings used from the recipe or command line:
//
//   cil-uwind-budget=10000
//
//   kiwic-finish=enable
//
//   kiwic-cil-dump=separately
//
//   kiwic-kcode-dump=enable
//
//   array-4d-name=KIWIARRAY4D
//
//   array-3d-name=KIWIARRAY3D
//
//   array-2d-name=KIWIARRAY2D
//
//   kiwi-dll=Kiwi.dll
//
//   kiwic-dll=Kiwic.dll
//
//   kiwic-zerolength-arrays=disable
//
//   kiwic-fpgaconsole-default=enable
//
//   postgen-optimise=enable
//
//   gtrace-loglevel=20
//
//   intcil-loglevel=20
//
//   firstpass-loglevel=20
//
//   root=$attributeroot
//
//   srcfile=test49.exe
//
//END OF KIWIC REPORT FILE
//

//----------------------------------------------------------

//Report from restructure2:::
//Offchip Load/Store (and other) Ports = Nothing to Report
//

//----------------------------------------------------------

//Report from restructure2:::
//Restructure Technology Settings
//*---------------------------+---------+---------------------------------------------------------------------------------*
//| Key                       | Value   | Description                                                                     |
//*---------------------------+---------+---------------------------------------------------------------------------------*
//| int_flr_mul               | 16000   |                                                                                 |
//| fp_fl_dp_div              | 5       |                                                                                 |
//| fp_fl_dp_add              | 4       |                                                                                 |
//| fp_fl_dp_mul              | 3       |                                                                                 |
//| fp_fl_sp_div              | 5       |                                                                                 |
//| fp_fl_sp_add              | 4       |                                                                                 |
//| fp_fl_sp_mul              | 3       |                                                                                 |
//| res2-loadstore-port-count | 0       |                                                                                 |
//| max_no_fp_muls            | 6       | Maximum number of adders and subtractors (or combos) to instantiate per thread. |
//| max_no_fp_muls            | 6       | Maximum number of f/p dividers to instantiate per thread.                       |
//| max_no_int_muls           | 3       | Maximum number of int multipliers to instantiate per thread.                    |
//| max_no_fp_divs            | 2       | Maximum number of f/p dividers to instantiate per thread.                       |
//| max_no_int_divs           | 2       | Maximum number of int dividers to instantiate per thread.                       |
//| res2-offchip-threshold    | 1000000 |                                                                                 |
//| res2-combrom-threshold    | 64      |                                                                                 |
//| res2-combram-threshold    | 32      |                                                                                 |
//| res2-regfile-threshold    | 8       |                                                                                 |
//*---------------------------+---------+---------------------------------------------------------------------------------*
//

//----------------------------------------------------------

//Report from restructure2:::
//PC codings points for xpc10 
//*---------------------+-----+-------------+------+------+-------+-----+-------------+------*
//| gb-flag/Pause       | eno | hwm         | root | exec | start | end | antecedants | next |
//*---------------------+-----+-------------+------+------+-------+-----+-------------+------*
//|   X0:"xpc10:start0" | 900 | hwm=0.0.0   | 0    | 0    | -     | -   | ---         | 1    |
//|   X1:"xpc10:1"      | 901 | hwm=0.5.0   | 1    | 6    | 2     | 6   | ---         | 7    |
//|   X2:"xpc10:2"      | 902 | hwm=0.0.0   | 7    | 7    | -     | -   | ---         | 8    |
//|   X4:"xpc10:4"      | 903 | hwm=0.5.0   | 8    | 13   | 9     | 13  | ---         | 14   |
//|   X8:"xpc10:8"      | 904 | hwm=0.0.0   | 14   | 14   | -     | -   | ---         | 15   |
//|   X16:"xpc10:16"    | 906 | hwm=0.5.0   | 15   | 20   | 16    | 20  | ---         | 7    |
//|   X16:"xpc10:16"    | 905 | hwm=0.0.0   | 15   | 15   | -     | -   | ---         | 21   |
//|   X32:"xpc10:32"    | 907 | hwm=0.0.0   | 21   | 21   | -     | -   | ---         | 22   |
//|   X64:"xpc10:64"    | 908 | hwm=0.5.0   | 22   | 27   | 23    | 27  | ---         | 22   |
//*---------------------+-----+-------------+------+------+-------+-----+-------------+------*
//

//----------------------------------------------------------

//Report from restructure2:::
//  Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X0:"xpc10:start0" 900 :  major_start_pcl=0   edge_private_start/end=-1/-1 exec=0 (dend=0)
//Simple greedy schedule for res2: Thread=xpc10 state=X0:"xpc10:start0"
//res2: Thread=xpc10 state=X0:"xpc10:start0"
//*-----+-----+---------+---------------------------------------------------------------*
//| pc  | eno | Phaser  | Work                                                          |
//*-----+-----+---------+---------------------------------------------------------------*
//| 0   | -   | R0 CTRL |                                                               |
//| 0   | 900 | R0 DATA |                                                               |
//| 0+E | 900 | W0 DATA | test49_volx te=te:0 scalarw(100)  PLI:Kiwi Demo - Test49 s... |
//*-----+-----+---------+---------------------------------------------------------------*
//

//----------------------------------------------------------

//Report from restructure2:::
//  Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1:"xpc10:1" 901 :  major_start_pcl=1   edge_private_start/end=2/6 exec=6 (dend=5)
//Simple greedy schedule for res2: Thread=xpc10 state=X1:"xpc10:1"
//res2: Thread=xpc10 state=X1:"xpc10:1"
//*-----+-----+---------+---------------------------------------------------------------------------------------------*
//| pc  | eno | Phaser  | Work                                                                                        |
//*-----+-----+---------+---------------------------------------------------------------------------------------------*
//| 1   | -   | R0 CTRL |                                                                                             |
//| 1   | 901 | R0 DATA | fpcvt10 te=te:1 cvt(test49_volx)                                                            |
//| 2   | 901 | R1 DATA |                                                                                             |
//| 3   | 901 | R2 DATA | CVFPMULTIPLIER10 te=te:3 *fixed-func-ALU*(C64f(test49_volx), 3330.2)                        |
//| 4   | 901 | R3 DATA |                                                                                             |
//| 5   | 901 | R4 DATA |                                                                                             |
//| 6   | 901 | R5 DATA |                                                                                             |
//| 6+E | 901 | W0 DATA | Ttte0.5_V_1 te=te:6 scalarw(E1) Ttte0.5_V_0 te=te:6 scalarw(0)  PLI:Kiwi Demo - Test49 p... |
//*-----+-----+---------+---------------------------------------------------------------------------------------------*
//

//----------------------------------------------------------

//Report from restructure2:::
//  Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2:"xpc10:2" 902 :  major_start_pcl=7   edge_private_start/end=-1/-1 exec=7 (dend=0)
//Simple greedy schedule for res2: Thread=xpc10 state=X2:"xpc10:2"
//res2: Thread=xpc10 state=X2:"xpc10:2"
//*-----+-----+---------+--------------------------------------------------------------------*
//| pc  | eno | Phaser  | Work                                                               |
//*-----+-----+---------+--------------------------------------------------------------------*
//| 7   | -   | R0 CTRL |                                                                    |
//| 7   | 902 | R0 DATA |                                                                    |
//| 7+E | 902 | W0 DATA | Ttte0.5_V_2 te=te:7 scalarw(Cf(Ttte0.5_V_1))  PLI:data %u  qfp0=%F |
//*-----+-----+---------+--------------------------------------------------------------------*
//

//----------------------------------------------------------

//Report from restructure2:::
//  Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4:"xpc10:4" 903 :  major_start_pcl=8   edge_private_start/end=9/13 exec=13 (dend=5)
//Simple greedy schedule for res2: Thread=xpc10 state=X4:"xpc10:4"
//res2: Thread=xpc10 state=X4:"xpc10:4"
//*------+-----+---------+-------------------------------------------------------------------------------*
//| pc   | eno | Phaser  | Work                                                                          |
//*------+-----+---------+-------------------------------------------------------------------------------*
//| 8    | -   | R0 CTRL |                                                                               |
//| 8    | 903 | R0 DATA | fpcvt12 te=te:8 cvt(Ttte0.5_V_2) fpcvt14 te=te:8 cvt(Ttte0.5_V_0)             |
//| 9    | 903 | R1 DATA |                                                                               |
//| 10   | 903 | R2 DATA | CVFPMULTIPLIER12 te=te:10 *fixed-func-ALU*(7.12345f, Cf(Ttte0.5_V_0))         |
//| 11   | 903 | R3 DATA |                                                                               |
//| 12   | 903 | R4 DATA |                                                                               |
//| 13   | 903 | R5 DATA |                                                                               |
//| 13+E | 903 | W0 DATA | Ttte0.5_V_4 te=te:13 scalarw(C(Ttte0.5_V_2)) Ttte0.5_V_3 te=te:13 scalarw(E2) |
//*------+-----+---------+-------------------------------------------------------------------------------*
//

//----------------------------------------------------------

//Report from restructure2:::
//  Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"xpc10:8" 904 :  major_start_pcl=14   edge_private_start/end=-1/-1 exec=14 (dend=0)
//Simple greedy schedule for res2: Thread=xpc10 state=X8:"xpc10:8"
//res2: Thread=xpc10 state=X8:"xpc10:8"
//*------+-----+---------+------------------------------*
//| pc   | eno | Phaser  | Work                         |
//*------+-----+---------+------------------------------*
//| 14   | -   | R0 CTRL |                              |
//| 14   | 904 | R0 DATA |                              |
//| 14+E | 904 | W0 DATA |  PLI:                  qf... |
//*------+-----+---------+------------------------------*
//

//----------------------------------------------------------

//Report from restructure2:::
//  Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16:"xpc10:16" 906 :  major_start_pcl=15   edge_private_start/end=16/20 exec=20 (dend=5)
//,   Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16:"xpc10:16" 905 :  major_start_pcl=15   edge_private_start/end=-1/-1 exec=15 (dend=0)
//Simple greedy schedule for res2: Thread=xpc10 state=X16:"xpc10:16"
//res2: Thread=xpc10 state=X16:"xpc10:16"
//*------+-----+---------+------------------------------------------------------------------------------*
//| pc   | eno | Phaser  | Work                                                                         |
//*------+-----+---------+------------------------------------------------------------------------------*
//| 15   | -   | R0 CTRL |                                                                              |
//| 15   | 905 | R0 DATA |                                                                              |
//| 15+E | 905 | W0 DATA | Ttte0.5_V_0 te=te:15 scalarw(1+Ttte0.5_V_0)  PLI:Kiwi Demo - Test49 p...     |
//| 15   | 906 | R0 DATA | fpcvt16 te=te:15 cvt(E3)                                                     |
//| 16   | 906 | R1 DATA |                                                                              |
//| 17   | 906 | R2 DATA | CVFPMULTIPLIER14 te=te:17 *fixed-func-ALU*(3330.2, E4)                       |
//| 18   | 906 | R3 DATA |                                                                              |
//| 19   | 906 | R4 DATA |                                                                              |
//| 20   | 906 | R5 DATA |                                                                              |
//| 20+E | 906 | W0 DATA | Ttte0.5_V_1 te=te:20 scalarw(E5) Ttte0.5_V_0 te=te:20 scalarw(1+Ttte0.5_V_0) |
//*------+-----+---------+------------------------------------------------------------------------------*
//

//----------------------------------------------------------

//Report from restructure2:::
//  Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X32:"xpc10:32" 907 :  major_start_pcl=21   edge_private_start/end=-1/-1 exec=21 (dend=0)
//Simple greedy schedule for res2: Thread=xpc10 state=X32:"xpc10:32"
//res2: Thread=xpc10 state=X32:"xpc10:32"
//*------+-----+---------+---------------------------------*
//| pc   | eno | Phaser  | Work                            |
//*------+-----+---------+---------------------------------*
//| 21   | -   | R0 CTRL |                                 |
//| 21   | 907 | R0 DATA |                                 |
//| 21+E | 907 | W0 DATA | Ttte0.6_V_1 te=te:21 scalarw(0) |
//*------+-----+---------+---------------------------------*
//

//----------------------------------------------------------

//Report from restructure2:::
//  Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X64:"xpc10:64" 908 :  major_start_pcl=22   edge_private_start/end=23/27 exec=27 (dend=5)
//Simple greedy schedule for res2: Thread=xpc10 state=X64:"xpc10:64"
//res2: Thread=xpc10 state=X64:"xpc10:64"
//*------+-----+---------+-------------------------------------------------------------------------------------------------------------------------------------*
//| pc   | eno | Phaser  | Work                                                                                                                                |
//*------+-----+---------+-------------------------------------------------------------------------------------------------------------------------------------*
//| 22   | -   | R0 CTRL |                                                                                                                                     |
//| 22   | 908 | R0 DATA | CVFPMULTIPLIER16 te=te:22 *fixed-func-ALU*(100, E6) CVFPADDER12 te=te:22 *fixed-func-ALU*(100, E7) CVFPADDER10 te=te:22 *fixed-fun\ |
//|      |     |         | c-ALU*(-100.0, E8) CVFPDIVIDER10 te=te:22 *fixed-func-ALU*(E9, 100)                                                                 |
//| 23   | 908 | R1 DATA |                                                                                                                                     |
//| 24   | 908 | R2 DATA |                                                                                                                                     |
//| 25   | 908 | R3 DATA |                                                                                                                                     |
//| 26   | 908 | R4 DATA |                                                                                                                                     |
//| 27   | 908 | R5 DATA |                                                                                                                                     |
//| 27+E | 908 | W0 DATA | Ttte0.6_V_1 te=te:27 scalarw(1+Ttte0.6_V_1)  PLI:phase1: data %u  is ...  PLI:GSAI:hpr_sysexit  PLI:Test49 done.  PLI:Kiwi Demo - \ |
//|      |     |         | Test49 p...                                                                                                                         |
//*------+-----+---------+-------------------------------------------------------------------------------------------------------------------------------------*
//

//----------------------------------------------------------

//Report from verilog_render:::
//1 vectors of width 5
//
//33 vectors of width 1
//
//21 vectors of width 64
//
//12 vectors of width 32
//
//6 array locations of width 64
//
//96 bits in scalar variables
//
//Total state bits in module = 2246 bits.
//
//619 continuously assigned (wire/non-state) bits 
//
//Total number of leaf cells = 0
//
// eof (HPR L/S Verilog)