// VNL output from CBG Lambda module tempmod(clk, reset, irq); input clk, reset, irq; wire [13:0] OCODE; reg [4:0] PCH; reg [7:0] PRESCALE; reg [7:0] W; reg [11:0] TOS3; reg [11:0] TOS2; reg [11:0] TOS1; reg [11:0] TOS; reg [7:0] TRIS; reg [7:0] OPTION; reg [7:0] ADCON1; reg [7:0] U5; reg [7:0] U4; reg [7:0] U3; reg [7:0] U2; reg [7:0] U1; reg [7:0] U0; reg [7:0] ADCON0; reg [7:0] INTCON; reg [7:0] ADRES; reg [7:0] PCLATH; reg [7:0] WDT; reg [7:0] GPIO; reg [7:0] FSR; reg [7:0] STATUS; reg [7:0] PCL; reg [7:0] TMR0; always @(posedge clk ) begin begin CPUREG_PCH <=((( MMREGS_PCL |( CPUREG_PCH <>h8); MMREGS_PCL <=((( MMREGS_PCL |( CPUREG_PCH <>h8); MMREGS_PCL <=(((( MMREGS_PCL |( CPUREG_PCH <>h8); MMREGS_PCL <=(((( MMREGS_PCL |( CPUREG_PCH <>h7); end if ( op-monadic &( op-monadic &( op-monadic &((h200==( OCODE &h3f00))&((he00==( OCODE &h3f00))&((h600==( OCODE &h3f00))&((h1000==( OCODE &h3c00))&((h1400==( OCODE &h3c00))&((h1800==( OCODE &h3c00))&((h1c00==( OCODE &h3c00))&((h3e00==( OCODE &h3f00))&((h3900==( OCODE &h3f00))&((h2000==( OCODE &h3800))&((h64==( OCODE &h3fff))&((h2800==( OCODE &h3800))&((h3800==( OCODE &h3f00))&((h3000==( OCODE &h3f00))&((h9==( OCODE &h3fff))&((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1))))))))))))))))))))))) begin h0<=((( (( OCODE &h7f)==h0) ?h0 :h0>>h1)|(( STATUS &h1)<>h4)|( (( OCODE &h7f)==h0) ?h0 :h0<>h8); MMREGS_PCL <=(((( MMREGS_PCL |( CPUREG_PCH <>h8); MMREGS_PCL <=(((( MMREGS_PCL |( CPUREG_PCH <>h7); end if ((( OCODE &h7f)==h0)&( op-monadic &( op-monadic &((h200==( OCODE &h3f00))&((he00==( OCODE &h3f00))&((h600==( OCODE &h3f00))&((h1000==( OCODE &h3c00))&((h1400==( OCODE &h3c00))&((h1800==( OCODE &h3c00))&((h1c00==( OCODE &h3c00))&((h3e00==( OCODE &h3f00))&((h3900==( OCODE &h3f00))&((h2000==( OCODE &h3800))&((h64==( OCODE &h3fff))&((h2800==( OCODE &h3800))&((h3800==( OCODE &h3f00))&((h3000==( OCODE &h3f00))&((h9==( OCODE &h3fff))&((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1))))))))))))))))))))))) begin h0<=((( (( OCODE &h7f)==h0) ?h0 :h0>>h1)|(( STATUS &h1)<>h4)|( (( OCODE &h7f)==h0) ?h0 :h0<>(( OCODE >>h7)&h7))))); if ( op-monadic &( op-monadic &((h1c00==( OCODE &h3c00))&((h3e00==( OCODE &h3f00))&((h3900==( OCODE &h3f00))&((h2000==( OCODE &h3800))&((h64==( OCODE &h3fff))&((h2800==( OCODE &h3800))&((h3800==( OCODE &h3f00))&((h3000==( OCODE &h3f00))&((h9==( OCODE &h3fff))&((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1)))))))))))))))) begin CPUREG_PCH <=(((( MMREGS_PCL |( CPUREG_PCH <>h8); MMREGS_PCL <=(((( MMREGS_PCL |( CPUREG_PCH <>h8); MMREGS_PCL <=(((( MMREGS_PCL |( CPUREG_PCH <>h8); MMREGS_PCL <=(((( MMREGS_PCL |( CPUREG_PCH <>h7); end if ( op-monadic &( op-monadic &((h200==( OCODE &h3f00))&((he00==( OCODE &h3f00))&((h600==( OCODE &h3f00))&((h1000==( OCODE &h3c00))&((h1400==( OCODE &h3c00))&((h1800==( OCODE &h3c00))&((h1c00==( OCODE &h3c00))&((h3e00==( OCODE &h3f00))&((h3900==( OCODE &h3f00))&((h2000==( OCODE &h3800))&((h64==( OCODE &h3fff))&((h2800==( OCODE &h3800))&((h3800==( OCODE &h3f00))&((h3000==( OCODE &h3f00))&((h9==( OCODE &h3fff))&((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1)))))))))))))))))))))) begin CPUREG_W <=((( (( OCODE &h7f)==h0) ?h0 :h0>>h1)|(( STATUS &h1)<>h4)|( (( OCODE &h7f)==h0) ?h0 :h0<>(( OCODE >>h7)&h7))))); if ( op-monadic &( op-monadic &((h1c00==( OCODE &h3c00))&((h3e00==( OCODE &h3f00))&((h3900==( OCODE &h3f00))&((h2000==( OCODE &h3800))&((h64==( OCODE &h3fff))&((h2800==( OCODE &h3800))&((h3800==( OCODE &h3f00))&((h3000==( OCODE &h3f00))&((h9==( OCODE &h3fff))&((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1))))))))))))))))NULL if ( op-monadic &( op-monadic &((h3e00==( OCODE &h3f00))&((h3900==( OCODE &h3f00))&((h2000==( OCODE &h3800))&((h64==( OCODE &h3fff))&((h2800==( OCODE &h3800))&((h3800==( OCODE &h3f00))&((h3000==( OCODE &h3f00))&((h9==( OCODE &h3fff))&((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1))))))))))))))) begin CPUREG_PCH <=(((( MMREGS_PCL |( CPUREG_PCH <>h8); MMREGS_PCL <=(((( MMREGS_PCL |( CPUREG_PCH <>h8); MMREGS_PCL <=(( OCODE &h7ff)&hff); end if ( op-monadic &((h2800==( OCODE &h3800))&((h3800==( OCODE &h3f00))&((h3000==( OCODE &h3f00))&((h9==( OCODE &h3fff))&((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1)))))))))) begin MMREGS_WDT <=h0; CPUREG_PRESCALE <=h0; end if ( op-monadic &((h3800==( OCODE &h3f00))&((h3000==( OCODE &h3f00))&((h9==( OCODE &h3fff))&((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1))))))))) begin CPUREG_PCH <=(( OCODE &h7ff)>>h8); MMREGS_PCL <=(( OCODE &h7ff)&hff); end if ( op-monadic &((h3000==( OCODE &h3f00))&((h9==( OCODE &h3fff))&((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1)))))))) begin CPUREG_W <=(hff&(( OCODE &hff)| CPUREG_W )); STATUS[1]<= (h0==(hff&(( OCODE &hff)| CPUREG_W ))) ?h1 :h0; end if ( op-monadic &((h9==( OCODE &h3fff))&((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1))))))) CPUREG_W <=( OCODE &hff); if ( op-monadic &((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1)))))) begin begin begin CPUREG_PCH <=( CPUREG_TOS >>h8); MMREGS_PCL <=( CPUREG_TOS &hff); end CPUREG_TOS <= CPUREG_TOS1 ; CPUREG_TOS1 <= CPUREG_TOS2 ; end INTCON[1]<=h1; end if ( op-monadic &((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1))))) begin begin CPUREG_PCH <=( CPUREG_TOS >>h8); MMREGS_PCL <=( CPUREG_TOS &hff); end CPUREG_TOS <= CPUREG_TOS1 ; CPUREG_TOS1 <= CPUREG_TOS2 ; end if ( op-monadic &((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1)))) begin CPUREG_W <=( OCODE &hff); begin CPUREG_PCH <=( CPUREG_TOS >>h8); MMREGS_PCL <=( CPUREG_TOS &hff); end CPUREG_TOS <= CPUREG_TOS1 ; CPUREG_TOS1 <= CPUREG_TOS2 ; end if ( op-monadic &((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1))) begin MMREGS_WDT <=h0; STATUS[1]<=h0; end if ( op-monadic &((h3a00==( OCODE &h3f00))&h1)) begin CPUREG_W <=(hff&(( OCODE &hff)- CPUREG_W )); STATUS[1]<= (h0==(hff&(( OCODE &hff)- CPUREG_W ))) ?h1 :h0; end if ( op-monadic &h1) begin CPUREG_W <=(hff&(( OCODE &hff)^ CPUREG_W )); STATUS[1]<= (h0==(hff&(( OCODE &hff)^ CPUREG_W ))) ?h1 :h0; end if ((h700==( OCODE &h3f00))&((h500==( OCODE &h3f00))&((h180==( OCODE &h3f00))&((h100==( OCODE &h3fff))&((h900==( OCODE &h3f00))&((h300==( OCODE &h3f00))&((hb00==( OCODE &h3f00))&((ha00==( OCODE &h3f00))&((hf00==( OCODE &h3f00))&((h400==( OCODE &h3f00))&((h800==( OCODE &h3f00))&((h800==( OCODE &h3f80))&((h80==( OCODE &h3f80))&((h0==( OCODE &h3fff))&((hd00==( OCODE &h3f00))&((hc00==( OCODE &h3f00))&((h200==( OCODE &h3f00))&((he00==( OCODE &h3f00))&((h600==( OCODE &h3f00))&((h1000==( OCODE &h3c00))&((h1400==( OCODE &h3c00))&((h1800==( OCODE &h3c00))&((h1c00==( OCODE &h3c00))&((h3e00==( OCODE &h3f00))&((h3900==( OCODE &h3f00))&((h2000==( OCODE &h3800))&((h64==( OCODE &h3fff))&((h2800==( OCODE &h3800))&((h3800==( OCODE &h3f00))&((h3000==( OCODE &h3f00))&((h9==( OCODE &h3fff))&((h8==( OCODE &h3fff))&((h3400==( OCODE &h3f00))&((h63==( OCODE &h3fff))&((h3c00==( OCODE &h3f00))&((h3a00==( OCODE &h3f00))&h1))))))))))))))))))))))))))))))))))))h0 end assign OCODE = (h771==( MMREGS_PCL |( CPUREG_PCH <