NEXT (Join Calculus)
ACS P35-16/17 SoC D/M Slide Pack 3.2 (High-Level Synthesis)
Higher-level: Behavioural or Declarative ?
Beyond Pure RTL: Behavioural descriptions of hardware.
More-advanced behavioural specification:
A Simple Worked Example: Classical HLS of Multiply
Multiplier Answer (2)
HLS Compiler Operational Phases
Adopting a Suitable Coding Style for HLS
HLS Synthesisable Subset.
Pipelined Schedulling - One Basic Block
Pipelined Schedulling - Between Basic Blocks
Functional Unit (FU) Block Properties
Discovering Parallelism: Classical HLS Paradigms
Memory Banking and Widening
Polyhedral Address Mapping
Kiwi : Compiling Concurrent Programs to Hardware
Classical High-Level Synthesis Example: Kiwi compilation of Sieve of Eratosthenes.
Static versus Dynamic Scheduling
Locally-Static, Globally-Dynamic Schedulling
Shortcomings of Verilog and VHDL as Algorithmic Expression Languages
Motivation To Adopt HLS
Other Expression forms: Channel Communication
Other Expression forms: Hardware Construction Languages
Other Expression forms: Logic Synthesis from Guarded Atomic Actions (Bluespec)
Classical Imperative/Behavioural H/L Synthesis Summary
HLS Expression forms: Behavioural using a Thread or Threads
Synopsys Behavioural Compiler
Expression forms: Declarative Specifications
Synthesis from Formal Specification
Synthesis/Refinement from Formal Specifications
Synthesis from Rules (SAT-based idea).
Synthesis from Cross-Product: Tool Flow:
Synthesis from Cross-Product (Greaves/Nam).
Expression forms: State charts and Graphical `languages'
All-forms High-level Synthesis Summary