DJIP Blocks - Toy IP Blocks.

A high-level model of the nominal processor:

• » CBG Nominal Processor - ISS CORE

The MPhil course work will use the OpenRISC or ARM processors and not this nominal processor.

A library of SystemC IP blocks that can be used by various targets in different classes:

• »Address Decoder
• »Bus Bridge (fragment of)
• »busmux.h
• »clock100.h
• »DMA Controller
• »Nominal Processor - Transacted to RTL
• »ram32.h - RTL style memory model

TLM (transactional-level modelling) versions of example IP blocks:

• » Example transport port (simpler than TLM2.0)
• » Nominal Processor - TLM version
• » tlm_busmux.h - TLM version
• » tlmram32.h - TLM style memory model

For simplicity, these TLM blocks do not use the TLM2 library, but they do have a TLM2-like standard payload that is passed between the TLM components.