Computer Laboratory

Computer Architecture Group

Recent Ph.D. thesies

Most of the Ph.D. thesies are available as Laboratory Technical Reports

  • Hongyan Xia, Capability memory protection for embedded systems, 2019
  • Alexandre Joannou, High-performance memory safety: optimizing the CHERI capability machine, 2019
  • Sam Ainsworth, Prefetching for complex memory access patterns, 2018
  • Colin Rothwell, Exploitation from malicious PCI Express peripherals, 2018
  • Robert Norton, Hardware support for compartmentalisation, 2015
  • Niall Murphy, Discovering and exploiting parallelism in DOACROSS loops, 2015
  • Ali Zaidi, Accelerating control-flow intensive code in spatial hardware, 2015
  • Jonathan Woodruff, CHERI: A RISC capability machine for practical memory safety, 2014
  • Paul Fox, Massively parallel neural computation, 2013
  • Greg Chadwick, Communication centric, multi-core, fine-grained processor architecture, 2012
  • Meredydd Luff, Communication for programmability and performance on multi-core processors, 2012
  • Charlie Reams, Modelling energy efficiency for computation, 2012
  • Nick Barrow-Williams, Proximity Coherence for chip-multiprocessors, 2011
  • Daniel Greenfield, Rentian Locality in Chip Multiprocessors, 2010
  • A. Theodore Markettos, Active Electromagnetics Attacks on Secure Hardware, 2010
  • Rosemary Francis, Exploring Networks-on-Chip for FPGAs, 2009
  • Philip Paul, Microelectronic security measures, 2009
  • Arnab Banerjee, Communication Flows in Power-Efficient Networks-on-Chips, 2008
  • Alban Rrustemi, Computing surfaces - a platform for scalable ubiquitous interactive displays, 2008
  • Matthew Johnson, A new approach to internet banking, 2008
  • Ian Caulfield, Complexity-Effective Superscalar Embedded Proessors Using Instruction-Level Distributed Processing, 2007
  • Simon Hollis, Pulse-based, On-chip Interconnect, 2007
  • Jacques Fournier, Vector Microprocessors for Cryptography, 2007
  • Huiyun Li, Security Evaluation at Design Time for Cryptographic Hardware, 2005
  • Scott Fairbanks, High Precision Timeing Using Self-Timed Circuits, 2004
  • Simon Frankau, Hardware Synthesis from a tream-processing functional language, 2004
  • Panit Watcharawitch, Multep: A Multithreaded Embedded Processor, 2003

Selected Publications

The CHERI project has a separate list of publications available on the main project webpage.

Many of these papers below are copyright of the respective journal or conference organizing body. These online copies are provided for your personal research use only.

2020

  • Marno van der Maas, Simon W. Moore, Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation CYSARM as part of ACM CCS, November 2020. Author's version
  • Naylor M, Moore S, Mokhov A, Thomas D, Beaumont J, Fleming S, Markettos AT, Bytheway T, Brown A. Termination detection for fine-grained message-passing architectures In Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors, 6-8 July 2020. PDF  Talk

2019

  • Hongyan Xia, Jonathan Woodruff, Sam Ainsworth, Nathaniel W. Filardo, Michael Roe, Alexander Richardson, Peter Rugg, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson, and Timothy M. Jones. CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety. In Proceedings of the 52nd IEEE/ACM International Symposium on Microarchitecture (IEEE MICRO 2019). Columbus, Ohio, USA, October 12-16, 2019. PDF DIO: 10.1145/3352460.3358288
  • Matthew Naylor, Simon W. Moore, David Thomas. Tinsel: a manythread overlay for FPGA clusters. International Conference on Field Programmable Logic and Applications (FPL) 9-13 September, 2019. (Open Access) DIO: 10.1109/FPL.2019.00066
  • Jonathan Woodruff, Alexandre Joannou, Hongyan Xia, Anthony Fox, Robert Norton, Thomas Bauereiss, David Chisnall, Brooks Davis, Khilan Gudka, Nathaniel W. Filardo, A. Theodore Markettos, Michael Roe, Peter G. Neumann, Robert N. M. Watson, Simon W. Moore. CHERI Concentrate: Practical Compressed Capabilities. IEEE Transaction on Computers, 31 April 2019, DOI: 10.1109/TC.2019.2914037 PDF
  • A. Theodore Markettos, Colin Rothwell, Brett F. Gutstein, Allison Pearce, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson. Thunderclap: Exploring Vulnerabilities in Operating-System IOMMU Protection from Untrustworthy Peripherals. 2019 NDSS Symposium (Network and Distributed System Security), San Diego, 24-27 February 2019 (PDF, Website) DOI: 10.14722/ndss.2019.23194

2018

  • Hongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, MichaelRoe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alex Richardson, Simon W. Moore, and Robert N. M. Watson. CheriRTOS: A Capability Model for Embedded Devices. Proceedings of the 2018 IEEE 36th International Conference on Computer Design (ICCD). Orlando, FL, USA, October 7-10, 2018. (PDF) DOI: 10.1109/ICCD.2018.00023

2017

  • Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W Moore, Alex Bradbury, Hongyan Xia, Robert NM Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey Son, A Theodore Markettos. Efficient Tagged Memory. IEEE 35th International Conference on Computer Design (ICCD), 2017 (PDF) DOI: 10.1109/ICCD.2017.112

2016

  • Robert N. M. Watson Robert Norton, Jonathan Woodruff, Alexandre Joannou, Simon W. Moore, Peter G. Neumann, Jonathan Anderson, David Chisnall, Nirav Dave, Brooks Davis, Khilan Gudka, Ben Laurie, A. Theodore Markettos, Ed Maste, Steven J. Murdoch, Michael Roe, Colin Rothwell, Stacey Son and Munraj Vadera. Fast Protection-Domain Crossing in the CHERI Capability-System Architecture, IEEE MICRO Journal, October 2016. [IEEE DOI: 10.1109/MM.2016.84, Open Access Archive]
  • Matthew Naylor, Simon W. Moore and Alan Mujumdar, A Consistency Checker for Memory Subsystem Traces, International Conference on Formal Methods in Computer-Aided Design (FMCAD), supported by IEEE & ACM, Mountain View, CA, USA, October 3-6, 2016. (PDF) DOI: 10.1109/FMCAD.2016.7886671

2015

  • Matthew Naylor and Simon W. Moore, A generic synthesisable test bench, 13th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), 21-23 September 2015, Austin, TX, USA, pp 128-137. (PDF) DOI: 10.1109/MEMCOD.2015.7340479
  • Robert N. M. Watson, Jonathan Woodruff, Peter G. Neumann, Simon W. Moore, Jonathan Anderson, David Chisnall, Nirav Dave, Brooks Davis, Khilan Gudka, Ben Laurie, Steven J. Murdoch, Robert Norton, Michael Roe, Stacey Son, Munraj Vadera, CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization, IEEE Symposium on Security and Privacy (aka Oakland), May 2015. (PDF) DOI: 10.1109/SP.2015.9

2014

  • Matthew Naylor and Simon W. Moore, Rapid codesign of a soft vector processor and its compiler, 24th International Conference on Field Programmable Logic and Applications (FPL2014), 2-4 September 2014. (PDF)
  • Paul J. Fox, A. Theodore Markettos, Simon W. Moore and Andrew W. Moore, Interconnect for commodity FPGA clusters: standardized or customized?, 24th International Conference on Field Programmable Logic and Applications (FPL2014), 2-4 September 2014. (PDF)
  • Paul J. Fox, A. Theodore Markettos and Simon W. Moore, Reliably Prototyping Large SoCs Using FPGA Clusters, 9th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'2014), 26-28 May 2014.
  • Jonathan Woodruff, Robert N. M. Watson, David Chisnall, Simon W. Moore, Jonathan Anderson, Brooks Davis, Ben Laurie, Peter G. Neumann, Robert Norton, and Michael Roe. The CHERI capability model: Revisiting RISC in an age of risk, Proceedings of the 41st International Symposium on Computer Architecture (ISCA 2014), 14–16 June, 2014, Minneapolis, MN, USA. (PDF)

2013

  • Yury Audzevich, Philip M. Watts, Andrew West, Alan Mujumdar, Simon W. Moore and Andrew W. Moore, Power Optimized Transceivers for Future Switched Networks, IEEE Transactions on VLSI Design, Vol. 22 Issue 10, pp. 2081-2092, September, 2013
  • Matthew Naylor, Paul J Fox, A Theodore Markettos and Simon W Moore, Managing the FPGA Memory Wall: custom computing or vector processing?, 23rd International Conference on Field Programmable Logic and Applications (FPL2013), September 2013. (PDF)

2012

  • Simone Campanoni, Timothy M. Jones, Glenn Holloway, Gu-Yeon Wei and David Brooks, The HELIX Project: Overview and Directions, In proceedings of the Design Automation Conference (DAC), June 2012.
  • Simone Campanoni, Timothy M. Jones, Glenn Holloway, Vijay Janapa Reddi, Gu-Yeon Wei and David Brooks, HELIX: Automatic Parallelization of Irregular Programs for Chip Multiprocessing, In proceedings of the International Symposium on Code Generation and Optimization (CGO), April 2012.
  • Karthik T. Sundararajan, Vasileious Porpodas, Timothy M. Jones, Nigel P. Topham and Björn Franke, Cooperative Partitioning: Energy-Efficient Cache Partitioning for High-Performance CMPs, In proceedings of the 18th International Symposium on High Performance Computer Architecture (HPCA-18), February 2012.
  • Javier Lira, Timothy M. Jones, Carlos Molina and Antonio González, The Migration Prefetcher: Anticipating Data Promotion in Dynamic NUCA Caches, In proceedings of the 7th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC) and ACM Transactions on Architecture and Code Optimization (TACO), Volume 8 Number 4, January 2012.

2011

  • Philip Watts, Nick Barrow-Williams and Simon Moore, Requirements of Low Power Photonic Networks for Distributed Shared Memory Computers, In proceedings of the optical Fiber Communication Conference and Expositions (OFC) and the National Fiber Optic Engineers Conference (NFOEC), 2011.
  • Christophe Dubach, Timothy M. Jones and Michael F.P. O'Boyle An Empirical Architecture-Centric Approach to Microarchitectural Design Space Exploration, In IEEE Transactions on Computers, Volume 60, Number 10, October 2011.
  • Karthik T. Sundararajan, Timothy M. Jones and Nigel Topham, Smart Cache: A Self Adaptive Cache Architecture for Energy Efficiency, In proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July 2011.
  • Timothy M. Jones, Sandro Bartolini, Jonas Maebe and Dominique Chanet, Link-Time Optimisation for Power Efficiency in a Tagless Instruction Cache, In proceedings of the International Symposium on Code Generation and Optimization (CGO), April 2011. Author's version
  • Timothy M. Jones, Michael F.P. O'Boyle, Jaume Abella and Antonio González, Compiler Directed Issue Queue Energy Reduction, In Transactions on High-Performance Embedded Architectures and Compilers IV, Lecture Notes in Computer Science, Volume 6760, 2011.

2010

  • Danielle S. Bassett, Daniel L. Greenfield, Andreas Meyer-Lindenberg, Daniel R. Weinberger, Simon W. Moore, Edward T. Bullmore, Efficient physical embedding of topologically complex information processing networks in brains and computer circuits, PLoS Computational Biology Journal, 2010. Journal Download
  • Nick Barrow-Williams, Chris Fensch and Simon Moore, Proximity Coherence for Chip Multiprocessors, In proceedings of International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2010.

2009

  • Daniel Greenfield and Simon Moore, Implications of Electronics Technology Trends to Algorithm Design, The Computer Journal, Volume 52, Issue 6, pp 690-698, doi:10.1093/comjnl/bxp013, April 2009. PDF version
  • Arnab Banerjee, Pascal Wolkotte, Robert Mullins, Simon Moore and Gerard Smit, An Energy and Performance Exploration of Network-on-Chip Architectures, In The IEEE Transactions on VLSI Systems Special Section on Networks-On-Chip, To appear in 2009.
  • Nick Barrow-Williams, Chris Fensch and Simon Moore, A Communication Characterisation of Splash-2 and Parsec, In Proceedings of the IEEE International Symposium on Workload Charecterization, October 2009. PDF version

2008

  • Arnab Banerjee, Pascal Wolkotte, Robert Mullins, Simon Moore and Gerard Smit, An Energy and Performance Exploration of Network-on-Chip Architectures, In The IEEE Trans. on VLSI Systems Special Section on Networks-On-Chip, to appear late 2008.
  • Daniel Greenfield and Simon Moore, Implications of Electronics Technology Trends to Algorithm Design, In Proceedings of BCS Visions of Computer Science, Sept 2008. PDF (slides PDF )
  • Daniel Greenfield and Simon Moore, Brief Announcement: Fractal Communication in Software Data Dependency Graphs, In Proceedings of the 20th Annual ACM Symp. on Parallel Algorithms and Architectures (SPAA), June 2008. PDF
  • Rosemary Francis, Simon Moore and Robert Mullins, A Network of Time-Division Multiplexed Wiring for FPGAs, In Proceedings of the 2nd Intl. Symp. on Networks-on-Chips (NOCS), April 2008. (slides PDF )
  • Simon Moore and Daniel Greenfield, The Next Resource War: Computation vs. Communication, In the 10th Intl. Workshop on System-Level Interconnect Prediction (SLIP), April 2008. PDF

2007

  • Arnab Banerjee, Robert Mullins and Simon Moore, A Power and Energy Exploration of Network-on-Chip Architectures, In Proceedings of the First Intl. Symp. on Networks-on-Chips (NOCS), May 2007.
  • Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee and Simon Moore, Implications of Rent's Rule for NoC Design and its Fault-Tolerance, In Proceedings of the First Intl. Symp. on Networks-on-Chips (NOCS), May 2007. Paper (slides PDF )
  • Robert Mullins and Simon Moore, Demystifying Data-Driven and Pausible Clocking Schemes In Proceedings of 13th IEEE Intl. Symp. on Asynchronous Circuits and Systems (ASYNC), March 2007.

2006

  • Robert Mullins, Minimising Dynamic Power Consumption in On-Chip Networks. In Proceedings of the Intl. Symp. on System-on-Chip, Tampere, Finland, November 2006.
  • S. Hollis and S.W. Moore, RasP: An area-efficient, on-chip network, In Proceedings of 24th International Conference on Computer Design (ICCD), Oct 2006.
  • Robert Mullins and Simon Moore, Demystifying Data-Driven and Pausible Clocking Schemes. In Proceedings of the 18th UK Asynchronous Forum, Newcastle, UK. September 2006. (Tutorial Slides - HTML (requires flash) / PPT / PDF )
  • J.J. Fournier and S.W. Moore, Hardware-software codesign of a vector co-processor for public key cryptography, 9th Euromicro Conference on Digital Systems Design, Croatia, August 2006
  • S. Hollis and S.W. Moore, An area-efficient pulse-based interconnect, Intl. Symposium on Circuits and Systems (ISCAS), May 2006.
  • P. Oikonomakos, J.J. Fournier and S.W. Moore, Implementing Cryptography on TFT Technology for Secure Display Applications, in the LNCS Proceedings of the 7th Smart Card Research and Advanced Application IFIP Conference (CARDIS'06), LNCS 3928 pp. 32-47, April 2006. PDF
  • P. Oikonomakos and S. Moore, An Asynchronous PLA with Improved Security Characteristics, 9th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (DSD06), Cavtat, Croatia 2006, pp 257-264. PDF
  • Huiyun Li, Security evaluation at design time for cryptographic hardware. Technical Report UCAM-CL-TR-665, University of Cambridge Computer Laboratory, April 2006.
  • Robert Mullins, Andrew West and Simon Moore, The Design and Implementation of a Low-Latency On-Chip Network. In Proceedings of the 11th Asia and South Pacific Design Automation Conference, January 2006. PDF / HTML (requires Flash) (slides PDF / PPT )
  • Simon Hollis and Simon Moore, An Asynchronous Interconnect Architecture for Device Security Enhancement. 19th International Conference on VLSI Design, January 2006. PDF

2005

  • J.J. Fournier and S.W. Moore, A vector approach to Cryptography Implementation. In the LNCS Proceedings of the 1st International Conference on Digital Rights Management Technologies Issues Challenges and Systems (DRMtics 2005), November 2005.
  • G.F. Roberts, R.V. Penty, I.H. White, A. West and S.W. Moore, Multi-wavelength data encoding for improved input power dynamic range in semiconductor optical amplifier switches. In the 18th Annual Meeting of the IEEE Lasers and Electro-optics society (LEOS), Sydney, Australia, October 2005.
  • H. Li, A. A. T. Markettos and S. W. Moore, A Security Evaluation Methodology for Smart Cards Against Electromagnetic Analysis. In proceedings of the 39th IEEE International Carnahan Conference on Security Technology (ICCST 2005), October 2005. PDF
  • H. Li, A. A. T. Markettos and S. W. Moore, Security Evaluation Against Electromagnetic Analysis at Design Time. Workshop on Cryptographic Hardware and Embedded Systems (CHES), September 2005. PDF
  • S. Fairbanks and S.W. Moore, Self-timed Circuitry for Global Clocking. In Proceedings of the 11th International Symposium on Asynchronous Circuits (ASYNC), March 2005. PDF

2004

  • Robert Mullins, Andrew West and Simon Moore, Low-Latency Virtual-Channel Routers for On-Chip Networks. In Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA), June, 2004. PS / PDF / HTML (requires Flash)
     (Also published in ACM SIGARCH Computer Architecture News, Vol. 32(2), pages 188- 197, 2004)
  • S. Fairbanks and S.W. Moore, High Precision Timing Signals Using Asynchronous Control Rings 10th International Symposium on Asynchronous Circuits, April 2004. PDF

2003

  • S. G. Frankau and A. Mycroft, Stream Processing Hardware from Functional Language Specifications, Proc. 36th Hawaii International Conference on System Sciences (HICSS 36), IEEE 2003 PDF
  • Simon Moore, Ross Anderson, Robert Mullins, George Taylor and Jacques Fournier, Balanced Self-Checking Asynchronous Logic for Smart Card Applications Microprocessors and Microsystems, Volume 27, Issue 9, October 2003, Pages 421-430. PDF
  • J. Fournier, H. Li, S.W. Moore, R.D. Mullins, G.S. Taylor, Security Evaluation of Asynchronous Circuits, Workshop on Cryptographic Hardware and Embedded Systems, September 2003
  • P. Watcharawitch and S.W. Moore, MulTEP: Multithreaded Embedded Processors, International Symposium on Low-Power and High-Speed Chips, Volume I, pp 355-361, April 2003.

2002

  • P. Watcharawitch and S.W. Moore, JMA: The Java-Multithreading Architecture for Embedded Systems, International Conference on Computer Design, pp 527--530, September 2002. PDF
  • Simon Moore, Ross Anderson, Paul Cunningham, Robert Mullins, George Taylor, Improving Smart Card Security using Self-timed Circuits, Eighth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2002. PDF
  • Simon Moore, George Taylor, Robert Mullins, Peter Robinson, Point-to-Point GALS Interconnect, Eighth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2002

2001-

  • S.W. Moore, Protecting Consumer Security Devices --- The Next 10 Years, published by Springer in LNCS 2140, Cannes, September 2001.
  • S.W. Moore, G.S. Taylor, P.A. Cunningham, R.D. Mullins and P.Robinson, Self Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems, In Proc. of the International Conference on Computer Design (ICCD), Austin Texas, September 2000. PDF