We have taken `maximum sustainable throughput' to be ``the maximum data rate that can be forwarded continuously arriving on a single VCI, given no switch contention or other problems''.
Due to the nature of the hardware however, the single VCI constraint is not a limiting one: the same rate could be sustained across many VCIs. Fabric contention resulting in NACKS obviously reduces the port controller throughput, so was ignored in this experiment. `Other problems' covers things like errors on the transmission line. Many million cells have been shipped without error, but when one does occur (usually artificially generated), the FPC2 currently attempts to print information about its occurrence. This distracts it from cell forwarding, and would affect results. During all of these experiments, no transmission line bit errors were ever detected.
All data rates quoted in this document refer to payload data rates i.e. 48 octet cells. This was done because it was thought to be more meaningful than quoting rates for cells with headers.
The maximum payload data rate of the TAXI transmission links is 87.3 Mb/s. Ideally, a port controller should be able to cell forward at this rate, and have some CPU time left over for connection management etc.
Before these experiments it was predicted that the bottleneck in cell forwarding was software running on the ARM CPU. When the rate of cells arriving exceeds the rate at which they can be processed, cells will back up in the FPC2's 2000 cell input buffer. If the buffer fills, this is detected. These experiments reveal that with faster ARM parts, this is not always the case.