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Lecturer: Dr I.A. Pratt
(ian.pratt@cl.cam.ac.uk)
No. of lectures: 12
Prerequisite course: Computer Design
Aims
This course examines the architecture and implementation of
state-of-the-art microprocessors and memory systems. It begins by
examining the different design goals that microprocessors are
developed for, and discusses the difficulties associated with making
objective performance comparisons.
Features of a number of popular Instruction Set Architectures are
compared and contrasted, with particular attention to their effects on
implementation and hence performance. The second half of the course
addresses micro-architecture implementation issues, examining how
Instruction Level Parallelism can be exploited through deep pipelining
and super-scalar techniques such as out-of-order execution. Finally,
issues in memory hierarchy design are explored.
Lectures
- Comparing architectures.
The technology curve. System versus chip performance. Speed:
MIPS, MHz, FLOPS, SPEC. Power. Price. Compatibility.
Features. [2 lectures]
- Instruction set architecture.
Amdahl's law and RISC principles. Byte sex. Word size. Stacks,
Accumulators and GPRs. Load-store versus
register-memory. Addressing modes. Code density. Sub-word and
un-aligned loads and stores. [2 lectures]
- Advanced pipelining.
The CPU performance equation. Structural hazards: long latency
instructions. Data hazards: result forwarding and delayed loads.
Control hazards: optimising branches, and avoiding branches.
Exceptions. [2 lectures]
- Super-scalar techniques.
Staticly scheduled and dynamic
out-of-order execution. Register renaming. [2 lectures]
- Instruction level parallelism.
The limits of ILP. Alternative architectures: VLIW, SMT
[2 lectures]
- Memory hierarchy.
Cache configurations. Latency versus bandwidth. Re-ordering
and coherence. Programming for caches. SMP cache coherency. Message
passing [2 lecture]
Objectives
At the end of the course students should
- appreciate the balance between implementation and architecture
in determining performance
- understand how quantitative analysis led to the convergence
towards RISC-like designs
- comprehend the issues associated with deeply-pipelined designs
- understand the operation of processors supporting out-of-order
execution
- be able to describe the difficulties associated with building
wide-issue machines, and have a basic understanding of the
alternatives to Instruction Level Parallelism
- appreciate the tradeoffs made by architects in the design of
memory hierarchies
Recommended books
Hennessy, J. & Patterson, D. (1996). Computer Architecture: a
Quantitative Approach (Chapters 1-5 in particular). Morgan Kaufmann
(2nd ed.).
Further reading and reference:
Tannenbaum, A.S. (1990). Structured Computer Organization.
Prentice-Hall (2nd ed.).
Van Someren, A. & Atack, C. (1994). The ARM RISC Chip: a
Programmer's Guide. Addison-Wesley.
Sites, R.L. (ed.) (1992). Alpha Architecture Reference Manual.
Digital Press.
Kane, G. & Heinrich, J. (1992). MIPS RISC
Architecture. Prentice-Hall.
Messmer, H. (1995). The Indispensable Pentium Book.
Addison-Wesley.
The CPU Info Center: http://infopad.eecs.berkeley.edu/CIC/tech/
Next: Natural Language Processing
Up: Lent Term 2002: Part
Previous: Additional Topics continued
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Christine Northeast
Tue Sep 4 09:34:31 BST 2001